[ia32] Move SSE unops into macro list
This is similar to x64, these SSE operations take 2 operands, and their AVX version also takes 2 operands. Bug: v8:11879 Change-Id: I98885a7b69f3b61ee89e713b5d7cf2f4fd2406db Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3169315 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/main@{#76943}
This commit is contained in:
Ng Zhi An
V8 LUCI CQ
parent
de1de7c3b8
commit
32253e897c
@ -2188,13 +2188,6 @@ void Assembler::cvtss2sd(XMMRegister dst, Operand src) {
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emit_sse_operand(dst, src);
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}
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void Assembler::cvtdq2ps(XMMRegister dst, Operand src) {
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EnsureSpace ensure_space(this);
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EMIT(0x0F);
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EMIT(0x5B);
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emit_sse_operand(dst, src);
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}
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void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
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EnsureSpace ensure_space(this);
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EMIT(0xF3);
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@ -2203,13 +2196,6 @@ void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
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emit_sse_operand(dst, src);
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}
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void Assembler::cvtps2pd(XMMRegister dst, XMMRegister src) {
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EnsureSpace ensure_space(this);
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EMIT(0x0F);
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EMIT(0x5A);
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emit_sse_operand(dst, src);
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}
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void Assembler::cvtpd2ps(XMMRegister dst, XMMRegister src) {
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EnsureSpace ensure_space(this);
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EMIT(0x66);
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@ -2234,27 +2220,6 @@ void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
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emit_sse_operand(dst, src);
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}
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void Assembler::rcpps(XMMRegister dst, Operand src) {
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EnsureSpace ensure_space(this);
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EMIT(0x0F);
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EMIT(0x53);
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emit_sse_operand(dst, src);
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}
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void Assembler::sqrtps(XMMRegister dst, Operand src) {
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EnsureSpace ensure_space(this);
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EMIT(0x0F);
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EMIT(0x51);
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emit_sse_operand(dst, src);
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}
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void Assembler::rsqrtps(XMMRegister dst, Operand src) {
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EnsureSpace ensure_space(this);
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EMIT(0x0F);
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EMIT(0x52);
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emit_sse_operand(dst, src);
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}
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void Assembler::cmpps(XMMRegister dst, Operand src, uint8_t cmp) {
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EnsureSpace ensure_space(this);
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EMIT(0x0F);
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@ -3206,6 +3171,14 @@ void Assembler::rorx(Register dst, Operand src, byte imm8) {
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EMIT(imm8);
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}
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void Assembler::sse_instr(XMMRegister dst, Operand src, byte escape,
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byte opcode) {
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EnsureSpace ensure_space(this);
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EMIT(escape);
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EMIT(opcode);
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emit_sse_operand(dst, src);
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}
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void Assembler::sse2_instr(XMMRegister dst, Operand src, byte prefix,
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byte escape, byte opcode) {
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EnsureSpace ensure_space(this);
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@ -899,12 +899,6 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
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void minss(XMMRegister dst, XMMRegister src) { minss(dst, Operand(src)); }
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void minss(XMMRegister dst, Operand src);
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void rcpps(XMMRegister dst, Operand src);
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void rcpps(XMMRegister dst, XMMRegister src) { rcpps(dst, Operand(src)); }
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void sqrtps(XMMRegister dst, Operand src);
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void sqrtps(XMMRegister dst, XMMRegister src) { sqrtps(dst, Operand(src)); }
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void rsqrtps(XMMRegister dst, Operand src);
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void rsqrtps(XMMRegister dst, XMMRegister src) { rsqrtps(dst, Operand(src)); }
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void haddps(XMMRegister dst, Operand src);
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void haddps(XMMRegister dst, XMMRegister src) { haddps(dst, Operand(src)); }
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void sqrtpd(XMMRegister dst, Operand src) {
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@ -961,12 +955,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
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void cvtss2sd(XMMRegister dst, XMMRegister src) {
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cvtss2sd(dst, Operand(src));
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}
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void cvtdq2ps(XMMRegister dst, XMMRegister src) {
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cvtdq2ps(dst, Operand(src));
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}
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void cvtdq2ps(XMMRegister dst, Operand src);
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void cvtdq2pd(XMMRegister dst, XMMRegister src);
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void cvtps2pd(XMMRegister dst, XMMRegister src);
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void cvtpd2ps(XMMRegister dst, XMMRegister src);
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void cvttps2dq(XMMRegister dst, XMMRegister src) {
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cvttps2dq(dst, Operand(src));
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@ -1290,20 +1279,6 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
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}
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void vss(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
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void vrcpps(XMMRegister dst, XMMRegister src) { vrcpps(dst, Operand(src)); }
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void vrcpps(XMMRegister dst, Operand src) {
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vinstr(0x53, dst, xmm0, src, kNone, k0F, kWIG);
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}
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void vsqrtps(XMMRegister dst, XMMRegister src) { vsqrtps(dst, Operand(src)); }
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void vsqrtps(XMMRegister dst, Operand src) {
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vinstr(0x51, dst, xmm0, src, kNone, k0F, kWIG);
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}
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void vrsqrtps(XMMRegister dst, XMMRegister src) {
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vrsqrtps(dst, Operand(src));
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}
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void vrsqrtps(XMMRegister dst, Operand src) {
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vinstr(0x52, dst, xmm0, src, kNone, k0F, kWIG);
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}
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void vhaddps(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
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vhaddps(dst, src1, Operand(src2));
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}
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@ -1444,18 +1419,9 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
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void vroundps(XMMRegister dst, XMMRegister src, RoundingMode mode);
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void vroundpd(XMMRegister dst, XMMRegister src, RoundingMode mode);
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void vcvtdq2ps(XMMRegister dst, XMMRegister src) {
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vcvtdq2ps(dst, Operand(src));
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}
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void vcvtdq2ps(XMMRegister dst, Operand src) {
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vinstr(0x5B, dst, xmm0, src, kNone, k0F, kWIG);
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}
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void vcvtdq2pd(XMMRegister dst, XMMRegister src) {
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vinstr(0xE6, dst, xmm0, src, kF3, k0F, kWIG);
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}
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void vcvtps2pd(XMMRegister dst, XMMRegister src) {
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vinstr(0x5A, dst, xmm0, src, kNone, k0F, kWIG);
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}
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void vcvtpd2ps(XMMRegister dst, XMMRegister src) {
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vinstr(0x5A, dst, xmm0, src, k66, k0F, kWIG);
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}
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@ -1696,6 +1662,23 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
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#undef PACKED_CMP_LIST
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// Other SSE and AVX instructions
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#define DECLARE_SSE_UNOP_AND_AVX(instruction, escape, opcode) \
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void instruction(XMMRegister dst, XMMRegister src) { \
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instruction(dst, Operand(src)); \
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} \
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void instruction(XMMRegister dst, Operand src) { \
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sse_instr(dst, src, 0x##escape, 0x##opcode); \
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} \
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void v##instruction(XMMRegister dst, XMMRegister src) { \
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v##instruction(dst, Operand(src)); \
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} \
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void v##instruction(XMMRegister dst, Operand src) { \
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vinstr(0x##opcode, dst, xmm0, src, kNone, k##escape, kWIG); \
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}
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SSE_UNOP_INSTRUCTION_LIST(DECLARE_SSE_UNOP_AND_AVX)
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#undef DECLARE_SSE_UNOP_AND_AVX
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#define DECLARE_SSE2_INSTRUCTION(instruction, prefix, escape, opcode) \
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void instruction(XMMRegister dst, XMMRegister src) { \
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instruction(dst, Operand(src)); \
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@ -1905,6 +1888,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
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inline void emit_disp(Label* L, Displacement::Type type);
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inline void emit_near_disp(Label* L);
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void sse_instr(XMMRegister dst, Operand src, byte prefix, byte opcode);
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void sse2_instr(XMMRegister dst, Operand src, byte prefix, byte escape,
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byte opcode);
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void ssse3_instr(XMMRegister dst, Operand src, byte prefix, byte escape1,
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@ -5,6 +5,14 @@
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#ifndef V8_CODEGEN_IA32_SSE_INSTR_H_
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#define V8_CODEGEN_IA32_SSE_INSTR_H_
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// SSE/SSE2 instructions whose AVX version has two operands.
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#define SSE_UNOP_INSTRUCTION_LIST(V) \
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V(sqrtps, 0F, 51) \
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V(rsqrtps, 0F, 52) \
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V(rcpps, 0F, 53) \
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V(cvtps2pd, 0F, 5A) \
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V(cvtdq2ps, 0F, 5B)
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#define SSE2_INSTRUCTION_LIST(V) \
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V(packsswb, 66, 0F, 63) \
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V(packssdw, 66, 0F, 6B) \
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