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[turbofan] IA: TruncateFloat64ToFloat32 supports mem operand

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BUG=
R=dcarney@chromium.org

Review URL: https://codereview.chromium.org/639283003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24541 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
dcarney@chromium.org 2014-10-13 07:12:57 +00:00
parent 52e156a866
commit 3396c2badd
11 changed files with 60 additions and 8 deletions
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2
src/compiler/ia32/code-generator-ia32.cc
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@ -354,7 +354,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ cvtss2sd(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
break;
case kSSECvtsd2ss:
__ cvtsd2ss(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
__ cvtsd2ss(i.OutputDoubleRegister(), i.InputOperand(0));
break;
case kSSEFloat64ToInt32:
__ cvttsd2si(i.OutputRegister(), i.InputOperand(0));

3
src/compiler/ia32/instruction-selector-ia32.cc
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@ -530,8 +530,7 @@ void InstructionSelector::VisitChangeFloat64ToUint32(Node* node) {
void InstructionSelector::VisitTruncateFloat64ToFloat32(Node* node) {
IA32OperandGenerator g(this);
// TODO(turbofan): IA32 SSE conversions should take an operand.
Emit(kSSECvtsd2ss, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)));
Emit(kSSECvtsd2ss, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
}

6
src/compiler/x64/code-generator-x64.cc
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@ -408,7 +408,11 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ cvtss2sd(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
break;
case kSSECvtsd2ss:
__ cvtsd2ss(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
if (instr->InputAt(0)->IsDoubleRegister()) {
__ cvtsd2ss(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
} else {
__ cvtsd2ss(i.OutputDoubleRegister(), i.InputOperand(0));
}
break;
case kSSEFloat64ToInt32:
if (instr->InputAt(0)->IsDoubleRegister()) {

3
src/compiler/x64/instruction-selector-x64.cc
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@ -651,8 +651,7 @@ void InstructionSelector::VisitChangeUint32ToUint64(Node* node) {
void InstructionSelector::VisitTruncateFloat64ToFloat32(Node* node) {
X64OperandGenerator g(this);
// TODO(turbofan): X64 SSE conversions should take an operand.
Emit(kSSECvtsd2ss, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)));
Emit(kSSECvtsd2ss, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
}

2
src/ia32/assembler-ia32.cc
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@ -1960,7 +1960,7 @@ void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
}
void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
void Assembler::cvtsd2ss(XMMRegister dst, const Operand& src) {
EnsureSpace ensure_space(this);
EMIT(0xF2);
EMIT(0x0F);

5
src/ia32/assembler-ia32.h
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@ -959,7 +959,10 @@ class Assembler : public AssemblerBase {
void cvtsi2sd(XMMRegister dst, Register src) { cvtsi2sd(dst, Operand(src)); }
void cvtsi2sd(XMMRegister dst, const Operand& src);
void cvtss2sd(XMMRegister dst, XMMRegister src);
void cvtsd2ss(XMMRegister dst, XMMRegister src);
void cvtsd2ss(XMMRegister dst, const Operand& src);
void cvtsd2ss(XMMRegister dst, XMMRegister src) {
cvtsd2ss(dst, Operand(src));
}
void addsd(XMMRegister dst, XMMRegister src);
void addsd(XMMRegister dst, const Operand& src);

10
src/x64/assembler-x64.cc
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@ -2761,6 +2761,16 @@ void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
}
void Assembler::cvtsd2ss(XMMRegister dst, const Operand& src) {
EnsureSpace ensure_space(this);
emit(0xF2);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x5A);
emit_sse_operand(dst, src);
}
void Assembler::cvtsd2si(Register dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit(0xF2);

1
src/x64/assembler-x64.h
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@ -1076,6 +1076,7 @@ class Assembler : public AssemblerBase {
void cvtss2sd(XMMRegister dst, XMMRegister src);
void cvtss2sd(XMMRegister dst, const Operand& src);
void cvtsd2ss(XMMRegister dst, XMMRegister src);
void cvtsd2ss(XMMRegister dst, const Operand& src);
void cvtsd2si(Register dst, XMMRegister src);
void cvtsd2siq(Register dst, XMMRegister src);

32
test/cctest/compiler/test-run-machops.cc
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@ -3320,6 +3320,38 @@ TEST(RunChangeFloat64ToUint32_spilled) {
}
TEST(RunTruncateFloat64ToFloat32_spilled) {
RawMachineAssemblerTester<uint32_t> m;
const int kNumInputs = 32;
int32_t magic = 0x786234;
double input[kNumInputs];
float result[kNumInputs];
Node* input_node[kNumInputs];
for (int i = 0; i < kNumInputs; i++) {
input_node[i] =
m.Load(kMachFloat64, m.PointerConstant(&input), m.Int32Constant(i * 8));
}
for (int i = 0; i < kNumInputs; i++) {
m.Store(kMachFloat32, m.PointerConstant(&result), m.Int32Constant(i * 4),
m.TruncateFloat64ToFloat32(input_node[i]));
}
m.Return(m.Int32Constant(magic));
for (int i = 0; i < kNumInputs; i++) {
input[i] = 0.1 + i;
}
CHECK_EQ(magic, m.Call());
for (int i = 0; i < kNumInputs; i++) {
CHECK_EQ(result[i], DoubleToFloat32(input[i]));
}
}
TEST(RunDeadChangeFloat64ToInt32) {
RawMachineAssemblerTester<int32_t> m;
const int magic = 0x88abcda4;

2
test/cctest/test-disasm-ia32.cc
View File

@ -389,6 +389,8 @@ TEST(DisasmIa320) {
// Move operation
__ movaps(xmm0, xmm1);
__ shufps(xmm0, xmm0, 0x0);
__ cvtsd2ss(xmm0, xmm1);
__ cvtsd2ss(xmm0, Operand(ebx, ecx, times_4, 10000));
// logic operation
__ andps(xmm0, xmm1);

2
test/cctest/test-disasm-x64.cc
View File

@ -380,6 +380,8 @@ TEST(DisasmX64) {
// Move operation
__ cvttss2si(rdx, Operand(rbx, rcx, times_4, 10000));
__ cvttss2si(rdx, xmm1);
__ cvtsd2ss(xmm0, xmm1);
__ cvtsd2ss(xmm0, Operand(rbx, rcx, times_4, 10000));
__ movaps(xmm0, xmm1);
// logic operation