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[ia32][wasm] Add F32x4 Abs/Neg

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Also refine SSES128Not

Change-Id: Ifb34055ed673e1a0f5842e99b10547b834b0d9d6
Reviewed-on: https://chromium-review.googlesource.com/867520
Reviewed-by: Bill Budge <bbudge@chromium.org>
Reviewed-by: Benedikt Meurer <bmeurer@chromium.org>
Commit-Queue: Jing Bao <jing.bao@intel.com>
Cr-Commit-Position: refs/heads/master@{#50634}
This commit is contained in:
jing.bao 2018-01-16 15:29:55 +08:00 committed by Commit Bot
parent ab943ce571
commit 34ae77e053
6 changed files with 80 additions and 16 deletions
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47
src/compiler/ia32/code-generator-ia32.cc
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@ -1663,6 +1663,50 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputOperand(2), i.InputInt8(1) << 4);
break;
}
case kSSEF32x4Abs: {
XMMRegister dst = i.OutputSimd128Register();
Operand src = i.InputOperand(0);
if (src.is_reg(dst)) {
__ pcmpeqd(kScratchDoubleReg, kScratchDoubleReg);
__ psrld(kScratchDoubleReg, 1);
__ andps(dst, kScratchDoubleReg);
} else {
__ pcmpeqd(dst, dst);
__ psrld(dst, 1);
__ andps(dst, src);
}
break;
}
case kAVXF32x4Abs: {
CpuFeatureScope avx_scope(tasm(), AVX);
__ vpcmpeqd(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg);
__ vpsrld(kScratchDoubleReg, kScratchDoubleReg, 1);
__ vandps(i.OutputSimd128Register(), kScratchDoubleReg,
i.InputOperand(0));
break;
}
case kSSEF32x4Neg: {
XMMRegister dst = i.OutputSimd128Register();
Operand src = i.InputOperand(0);
if (src.is_reg(dst)) {
__ pcmpeqd(kScratchDoubleReg, kScratchDoubleReg);
__ pslld(kScratchDoubleReg, 31);
__ xorps(dst, kScratchDoubleReg);
} else {
__ pcmpeqd(dst, dst);
__ pslld(dst, 31);
__ xorps(dst, src);
}
break;
}
case kAVXF32x4Neg: {
CpuFeatureScope avx_scope(tasm(), AVX);
__ vpcmpeqd(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg);
__ vpslld(kScratchDoubleReg, kScratchDoubleReg, 31);
__ vxorps(i.OutputSimd128Register(), kScratchDoubleReg,
i.InputOperand(0));
break;
}
case kSSEF32x4Add: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ addps(i.OutputSimd128Register(), i.InputOperand(1));
@ -2540,8 +2584,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
XMMRegister dst = i.OutputSimd128Register();
Operand src = i.InputOperand(0);
if (src.is_reg(dst)) {
__ movaps(kScratchDoubleReg, dst);
__ pcmpeqd(dst, dst);
__ pcmpeqd(kScratchDoubleReg, kScratchDoubleReg);
__ pxor(dst, kScratchDoubleReg);
} else {
__ pcmpeqd(dst, dst);

4
src/compiler/ia32/instruction-codes-ia32.h
View File

@ -121,6 +121,10 @@ namespace compiler {
V(AVXF32x4ExtractLane) \
V(SSEF32x4ReplaceLane) \
V(AVXF32x4ReplaceLane) \
V(SSEF32x4Abs) \
V(AVXF32x4Abs) \
V(SSEF32x4Neg) \
V(AVXF32x4Neg) \
V(SSEF32x4Add) \
V(AVXF32x4Add) \
V(SSEF32x4Sub) \

4
src/compiler/ia32/instruction-scheduler-ia32.cc
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@ -103,6 +103,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kAVXF32x4ExtractLane:
case kSSEF32x4ReplaceLane:
case kAVXF32x4ReplaceLane:
case kSSEF32x4Abs:
case kAVXF32x4Abs:
case kSSEF32x4Neg:
case kAVXF32x4Neg:
case kSSEF32x4Add:
case kAVXF32x4Add:
case kSSEF32x4Sub:

31
src/compiler/ia32/instruction-selector-ia32.cc
View File

@ -1853,11 +1853,16 @@ VISIT_ATOMIC_BINOP(Xor)
V(S128Or) \
V(S128Xor)
#define SIMD_UNOP_LIST(V) \
V(I32x4Neg) \
V(I16x8Neg) \
#define SIMD_INT_UNOP_LIST(V) \
V(I32x4Neg) \
V(I16x8Neg) \
V(I8x16Neg)
#define SIMD_OTHER_UNOP_LIST(V) \
V(F32x4Abs) \
V(F32x4Neg) \
V(S128Not)
#define SIMD_SHIFT_OPCODES(V) \
V(I32x4Shl) \
V(I32x4ShrS) \
@ -1892,11 +1897,6 @@ void InstructionSelector::VisitS128Zero(Node* node) {
Emit(kIA32S128Zero, g.DefineAsRegister(node));
}
void InstructionSelector::VisitS128Not(Node* node) {
IA32OperandGenerator g(this);
InstructionCode opcode = IsSupported(AVX) ? kAVXS128Not : kSSES128Not;
Emit(opcode, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
}
#define VISIT_SIMD_SPLAT(Type) \
void InstructionSelector::Visit##Type##Splat(Node* node) { \
@ -1947,13 +1947,22 @@ VISIT_SIMD_REPLACE_LANE(F32x4)
SIMD_SHIFT_OPCODES(VISIT_SIMD_SHIFT)
#undef VISIT_SIMD_SHIFT
#define VISIT_SIMD_UNOP(Opcode) \
#define VISIT_SIMD_INT_UNOP(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
IA32OperandGenerator g(this); \
Emit(kIA32##Opcode, g.DefineAsRegister(node), g.Use(node->InputAt(0))); \
}
SIMD_UNOP_LIST(VISIT_SIMD_UNOP)
#undef VISIT_SIMD_UNOP
SIMD_INT_UNOP_LIST(VISIT_SIMD_INT_UNOP)
#undef VISIT_SIMD_INT_UNOP
#define VISIT_SIMD_OTHER_UNOP(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
IA32OperandGenerator g(this); \
InstructionCode opcode = IsSupported(AVX) ? kAVX##Opcode : kSSE##Opcode; \
Emit(opcode, g.DefineAsRegister(node), g.Use(node->InputAt(0))); \
}
SIMD_OTHER_UNOP_LIST(VISIT_SIMD_OTHER_UNOP)
#undef VISIT_SIMD_OTHER_UNOP
#define VISIT_SIMD_BINOP(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \

6
src/compiler/instruction-selector.cc
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@ -2104,12 +2104,16 @@ void InstructionSelector::VisitF32x4SConvertI32x4(Node* node) {
void InstructionSelector::VisitF32x4UConvertI32x4(Node* node) {
UNIMPLEMENTED();
}
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS
// && !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS && \
!V8_TARGET_ARCH_MIPS64 && !V8_TARGET_ARCH_IA32
void InstructionSelector::VisitF32x4Abs(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Neg(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS
// && !V8_TARGET_ARCH_MIPS64
// && !V8_TARGET_ARCH_MIPS64 && !V8_TARGET_ARCH_IA32
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS && \
!V8_TARGET_ARCH_MIPS64 && !V8_TARGET_ARCH_X64

4
test/cctest/wasm/test-run-wasm-simd.cc
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@ -495,7 +495,7 @@ void RunF32x4UnOpTest(LowerSimd lower_simd, WasmOpcode simd_op,
}
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS || \
V8_TARGET_ARCH_MIPS64
V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_IA32
WASM_SIMD_TEST(F32x4Abs) {
RunF32x4UnOpTest(lower_simd, kExprF32x4Abs, std::abs);
}
@ -503,7 +503,7 @@ WASM_SIMD_TEST(F32x4Neg) {
RunF32x4UnOpTest(lower_simd, kExprF32x4Neg, Negate);
}
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS ||
// V8_TARGET_ARCH_MIPS64
// V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_IA32
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS || \
V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_X64