[turbofan] ARM64 support for inverted logical ops
Select ARM64 inverted rhs instructions (bic, orn, eon) for cases where the rhs input is inverted (using e/xor), and add some tests for this. Also, rename xor to eor in the ARM64 backend. BUG= R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/591383003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24188 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
m.m.capewell@googlemail.com
parent
ea97f413ee
commit
352733dca2
@ -189,6 +189,12 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
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case kArm64And32:
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__ And(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand32(1));
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break;
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case kArm64Bic:
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__ Bic(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
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break;
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case kArm64Bic32:
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__ Bic(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand32(1));
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break;
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case kArm64Mul:
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__ Mul(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
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break;
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@ -256,12 +262,24 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
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case kArm64Or32:
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__ Orr(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand32(1));
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break;
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case kArm64Xor:
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case kArm64Orn:
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__ Orn(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
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break;
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case kArm64Orn32:
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__ Orn(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand32(1));
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break;
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case kArm64Eor:
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__ Eor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
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break;
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case kArm64Xor32:
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case kArm64Eor32:
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__ Eor(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand32(1));
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break;
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case kArm64Eon:
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__ Eon(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
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break;
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case kArm64Eon32:
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__ Eon(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand32(1));
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break;
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case kArm64Sub:
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__ Sub(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
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break;
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@ -16,6 +16,8 @@ namespace compiler {
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V(Arm64Add32) \
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V(Arm64And) \
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V(Arm64And32) \
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V(Arm64Bic) \
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V(Arm64Bic32) \
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V(Arm64Cmp) \
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V(Arm64Cmp32) \
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V(Arm64Cmn) \
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@ -24,8 +26,12 @@ namespace compiler {
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V(Arm64Tst32) \
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V(Arm64Or) \
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V(Arm64Or32) \
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V(Arm64Xor) \
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V(Arm64Xor32) \
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V(Arm64Orn) \
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V(Arm64Orn32) \
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V(Arm64Eor) \
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V(Arm64Eor32) \
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V(Arm64Eon) \
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V(Arm64Eon32) \
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V(Arm64Sub) \
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V(Arm64Sub32) \
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V(Arm64Mul) \
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@ -58,8 +58,8 @@ static const MachInst2 kLogicalInstructions[] = {
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{&RawMachineAssembler::Word64And, "Word64And", kArm64And, kMachInt64},
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{&RawMachineAssembler::Word32Or, "Word32Or", kArm64Or32, kMachInt32},
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{&RawMachineAssembler::Word64Or, "Word64Or", kArm64Or, kMachInt64},
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{&RawMachineAssembler::Word32Xor, "Word32Xor", kArm64Xor32, kMachInt32},
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{&RawMachineAssembler::Word64Xor, "Word64Xor", kArm64Xor, kMachInt64}};
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{&RawMachineAssembler::Word32Xor, "Word32Xor", kArm64Eor32, kMachInt32},
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{&RawMachineAssembler::Word64Xor, "Word64Xor", kArm64Eor, kMachInt64}};
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// ARM64 logical immediates: contiguous set bits, rotated about a power of two
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@ -1049,7 +1049,7 @@ TEST_P(InstructionSelectorComparisonTest, WithImmediate) {
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// Compare with 0 are turned into tst instruction.
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if (imm == 0) continue;
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StreamBuilder m(this, type, type);
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m.Return((m.*cmp.constructor)(m.Parameter(0), BuildConstant(m, type, imm)));
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m.Return((m.*cmp.constructor)(BuildConstant(m, type, imm), m.Parameter(0)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(cmp.arch_opcode, s[0]->arch_opcode());
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@ -1122,6 +1122,166 @@ TEST_F(InstructionSelectorTest, Word64EqualWithZero) {
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}
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}
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// -----------------------------------------------------------------------------
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// Miscellaneous
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static const MachInst2 kLogicalWithNotRHSs[] = {
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{&RawMachineAssembler::Word32And, "Word32And", kArm64Bic32, kMachInt32},
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{&RawMachineAssembler::Word64And, "Word64And", kArm64Bic, kMachInt64},
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{&RawMachineAssembler::Word32Or, "Word32Or", kArm64Orn32, kMachInt32},
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{&RawMachineAssembler::Word64Or, "Word64Or", kArm64Orn, kMachInt64},
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{&RawMachineAssembler::Word32Xor, "Word32Xor", kArm64Eon32, kMachInt32},
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{&RawMachineAssembler::Word64Xor, "Word64Xor", kArm64Eon, kMachInt64}};
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typedef InstructionSelectorTestWithParam<MachInst2>
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InstructionSelectorLogicalWithNotRHSTest;
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TEST_P(InstructionSelectorLogicalWithNotRHSTest, Parameter) {
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const MachInst2 inst = GetParam();
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const MachineType type = inst.machine_type;
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// Test cases where RHS is Xor(x, -1).
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{
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StreamBuilder m(this, type, type, type);
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if (type == kMachInt32) {
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m.Return((m.*inst.constructor)(
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m.Parameter(0), m.Word32Xor(m.Parameter(1), m.Int32Constant(-1))));
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} else {
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ASSERT_EQ(kMachInt64, type);
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m.Return((m.*inst.constructor)(
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m.Parameter(0), m.Word64Xor(m.Parameter(1), m.Int64Constant(-1))));
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}
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(inst.arch_opcode, s[0]->arch_opcode());
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EXPECT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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{
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StreamBuilder m(this, type, type, type);
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if (type == kMachInt32) {
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m.Return((m.*inst.constructor)(
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m.Word32Xor(m.Parameter(0), m.Int32Constant(-1)), m.Parameter(1)));
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} else {
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ASSERT_EQ(kMachInt64, type);
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m.Return((m.*inst.constructor)(
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m.Word64Xor(m.Parameter(0), m.Int64Constant(-1)), m.Parameter(1)));
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}
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(inst.arch_opcode, s[0]->arch_opcode());
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EXPECT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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// Test cases where RHS is Not(x).
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{
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StreamBuilder m(this, type, type, type);
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if (type == kMachInt32) {
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m.Return(
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(m.*inst.constructor)(m.Parameter(0), m.Word32Not(m.Parameter(1))));
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} else {
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ASSERT_EQ(kMachInt64, type);
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m.Return(
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(m.*inst.constructor)(m.Parameter(0), m.Word64Not(m.Parameter(1))));
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}
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(inst.arch_opcode, s[0]->arch_opcode());
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EXPECT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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{
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StreamBuilder m(this, type, type, type);
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if (type == kMachInt32) {
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m.Return(
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(m.*inst.constructor)(m.Word32Not(m.Parameter(0)), m.Parameter(1)));
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} else {
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ASSERT_EQ(kMachInt64, type);
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m.Return(
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(m.*inst.constructor)(m.Word64Not(m.Parameter(0)), m.Parameter(1)));
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}
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(inst.arch_opcode, s[0]->arch_opcode());
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EXPECT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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}
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INSTANTIATE_TEST_CASE_P(InstructionSelectorTest,
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InstructionSelectorLogicalWithNotRHSTest,
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::testing::ValuesIn(kLogicalWithNotRHSs));
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TEST_F(InstructionSelectorTest, Word32NotWithParameter) {
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StreamBuilder m(this, kMachInt32, kMachInt32);
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m.Return(m.Word32Not(m.Parameter(0)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kArm64Not32, s[0]->arch_opcode());
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EXPECT_EQ(1U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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TEST_F(InstructionSelectorTest, Word64NotWithParameter) {
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StreamBuilder m(this, kMachInt64, kMachInt64);
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m.Return(m.Word64Not(m.Parameter(0)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kArm64Not, s[0]->arch_opcode());
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EXPECT_EQ(1U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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TEST_F(InstructionSelectorTest, Word32XorMinusOneWithParameter) {
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{
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StreamBuilder m(this, kMachInt32, kMachInt32);
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m.Return(m.Word32Xor(m.Parameter(0), m.Int32Constant(-1)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kArm64Not32, s[0]->arch_opcode());
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EXPECT_EQ(1U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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{
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StreamBuilder m(this, kMachInt32, kMachInt32);
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m.Return(m.Word32Xor(m.Int32Constant(-1), m.Parameter(0)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kArm64Not32, s[0]->arch_opcode());
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EXPECT_EQ(1U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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}
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TEST_F(InstructionSelectorTest, Word64XorMinusOneWithParameter) {
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{
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StreamBuilder m(this, kMachInt64, kMachInt64);
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m.Return(m.Word64Xor(m.Parameter(0), m.Int64Constant(-1)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kArm64Not, s[0]->arch_opcode());
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EXPECT_EQ(1U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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{
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StreamBuilder m(this, kMachInt64, kMachInt64);
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m.Return(m.Word64Xor(m.Int64Constant(-1), m.Parameter(0)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kArm64Not, s[0]->arch_opcode());
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EXPECT_EQ(1U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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}
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} // namespace compiler
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} // namespace internal
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} // namespace v8
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@ -267,45 +267,119 @@ void InstructionSelector::VisitStore(Node* node) {
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}
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template <typename Matcher>
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static void VisitLogical(InstructionSelector* selector, Node* node, Matcher* m,
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ArchOpcode opcode, bool left_can_cover,
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bool right_can_cover, ImmediateMode imm_mode) {
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Arm64OperandGenerator g(selector);
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// Map instruction to equivalent operation with inverted right input.
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ArchOpcode inv_opcode = opcode;
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switch (opcode) {
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case kArm64And32:
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inv_opcode = kArm64Bic32;
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break;
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case kArm64And:
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inv_opcode = kArm64Bic;
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break;
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case kArm64Or32:
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inv_opcode = kArm64Orn32;
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break;
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case kArm64Or:
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inv_opcode = kArm64Orn;
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break;
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case kArm64Eor32:
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inv_opcode = kArm64Eon32;
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break;
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case kArm64Eor:
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inv_opcode = kArm64Eon;
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break;
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default:
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UNREACHABLE();
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}
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// Select Logical(y, ~x) for Logical(Xor(x, -1), y).
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if ((m->left().IsWord32Xor() || m->left().IsWord64Xor()) && left_can_cover) {
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Matcher mleft(m->left().node());
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if (mleft.right().Is(-1)) {
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// TODO(all): support shifted operand on right.
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selector->Emit(inv_opcode, g.DefineAsRegister(node),
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g.UseRegister(m->right().node()),
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g.UseRegister(mleft.left().node()));
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return;
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}
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}
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// Select Logical(x, ~y) for Logical(x, Xor(y, -1)).
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if ((m->right().IsWord32Xor() || m->right().IsWord64Xor()) &&
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right_can_cover) {
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Matcher mright(m->right().node());
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if (mright.right().Is(-1)) {
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// TODO(all): support shifted operand on right.
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selector->Emit(inv_opcode, g.DefineAsRegister(node),
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g.UseRegister(m->left().node()),
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g.UseRegister(mright.left().node()));
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return;
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}
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}
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if (m->IsWord32Xor() && m->right().Is(-1)) {
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selector->Emit(kArm64Not32, g.DefineAsRegister(node),
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g.UseRegister(m->left().node()));
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} else if (m->IsWord64Xor() && m->right().Is(-1)) {
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selector->Emit(kArm64Not, g.DefineAsRegister(node),
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g.UseRegister(m->left().node()));
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} else {
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VisitBinop<Matcher>(selector, node, opcode, imm_mode);
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}
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}
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void InstructionSelector::VisitWord32And(Node* node) {
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VisitBinop<Int32BinopMatcher>(this, node, kArm64And32, kLogical32Imm);
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Int32BinopMatcher m(node);
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VisitLogical<Int32BinopMatcher>(
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this, node, &m, kArm64And32, CanCover(node, m.left().node()),
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CanCover(node, m.right().node()), kLogical32Imm);
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}
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void InstructionSelector::VisitWord64And(Node* node) {
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VisitBinop<Int64BinopMatcher>(this, node, kArm64And, kLogical64Imm);
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Int64BinopMatcher m(node);
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VisitLogical<Int64BinopMatcher>(
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this, node, &m, kArm64And, CanCover(node, m.left().node()),
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CanCover(node, m.right().node()), kLogical64Imm);
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}
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void InstructionSelector::VisitWord32Or(Node* node) {
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VisitBinop<Int32BinopMatcher>(this, node, kArm64Or32, kLogical32Imm);
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Int32BinopMatcher m(node);
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VisitLogical<Int32BinopMatcher>(
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this, node, &m, kArm64Or32, CanCover(node, m.left().node()),
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CanCover(node, m.right().node()), kLogical32Imm);
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}
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void InstructionSelector::VisitWord64Or(Node* node) {
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VisitBinop<Int64BinopMatcher>(this, node, kArm64Or, kLogical64Imm);
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Int64BinopMatcher m(node);
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VisitLogical<Int64BinopMatcher>(
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this, node, &m, kArm64Or, CanCover(node, m.left().node()),
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CanCover(node, m.right().node()), kLogical64Imm);
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}
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void InstructionSelector::VisitWord32Xor(Node* node) {
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Arm64OperandGenerator g(this);
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Int32BinopMatcher m(node);
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if (m.right().Is(-1)) {
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Emit(kArm64Not32, g.DefineAsRegister(node), g.UseRegister(m.left().node()));
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} else {
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VisitBinop<Int32BinopMatcher>(this, node, kArm64Xor32, kLogical32Imm);
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}
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VisitLogical<Int32BinopMatcher>(
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this, node, &m, kArm64Eor32, CanCover(node, m.left().node()),
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CanCover(node, m.right().node()), kLogical32Imm);
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}
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void InstructionSelector::VisitWord64Xor(Node* node) {
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Arm64OperandGenerator g(this);
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Int64BinopMatcher m(node);
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if (m.right().Is(-1)) {
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Emit(kArm64Not, g.DefineAsRegister(node), g.UseRegister(m.left().node()));
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} else {
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VisitBinop<Int64BinopMatcher>(this, node, kArm64Xor, kLogical32Imm);
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}
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VisitLogical<Int64BinopMatcher>(
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this, node, &m, kArm64Eor, CanCover(node, m.left().node()),
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CanCover(node, m.right().node()), kLogical64Imm);
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}
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