PPC: Use optimal seq for atomic load/store
R=joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com BUG= LOG=N Review-Url: https://codereview.chromium.org/2590543003 Cr-Commit-Position: refs/heads/master@{#41823}
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@ -764,36 +764,33 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) {
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DCHECK_EQ(LeaveRC, i.OutputRCBit()); \
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} while (0)
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#define ASSEMBLE_ATOMIC_LOAD_INTEGER(asm_instr, asm_instrx) \
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do { \
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Label done; \
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Register result = i.OutputRegister(); \
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AddressingMode mode = kMode_None; \
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MemOperand operand = i.MemoryOperand(&mode); \
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__ sync(); \
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if (mode == kMode_MRI) { \
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__ asm_instr(result, operand); \
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} else { \
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__ asm_instrx(result, operand); \
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} \
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__ bind(&done); \
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__ cmp(result, result); \
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__ bne(&done); \
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__ isync(); \
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#define ASSEMBLE_ATOMIC_LOAD_INTEGER(asm_instr, asm_instrx) \
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do { \
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Label done; \
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Register result = i.OutputRegister(); \
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AddressingMode mode = kMode_None; \
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MemOperand operand = i.MemoryOperand(&mode); \
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if (mode == kMode_MRI) { \
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__ asm_instr(result, operand); \
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} else { \
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__ asm_instrx(result, operand); \
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} \
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__ lwsync(); \
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} while (0)
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#define ASSEMBLE_ATOMIC_STORE_INTEGER(asm_instr, asm_instrx) \
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do { \
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size_t index = 0; \
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AddressingMode mode = kMode_None; \
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MemOperand operand = i.MemoryOperand(&mode, &index); \
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Register value = i.InputRegister(index); \
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__ sync(); \
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if (mode == kMode_MRI) { \
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__ asm_instr(value, operand); \
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} else { \
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__ asm_instrx(value, operand); \
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} \
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DCHECK_EQ(LeaveRC, i.OutputRCBit()); \
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#define ASSEMBLE_ATOMIC_STORE_INTEGER(asm_instr, asm_instrx) \
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do { \
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size_t index = 0; \
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AddressingMode mode = kMode_None; \
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MemOperand operand = i.MemoryOperand(&mode, &index); \
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Register value = i.InputRegister(index); \
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__ lwsync(); \
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if (mode == kMode_MRI) { \
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__ asm_instr(value, operand); \
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} else { \
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__ asm_instrx(value, operand); \
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} \
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__ sync(); \
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DCHECK_EQ(LeaveRC, i.OutputRCBit()); \
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} while (0)
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void CodeGenerator::AssembleDeconstructFrame() {
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