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[WASM] Eliminate SIMD boolean vector types.

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- Eliminates b1x4, b1x8, and b1x16 as distinct WASM types.
- All vector comparisons return v128 type.
- Eliminates b1xN and, or, xor, not.
- Selects take a v128 mask vector and are now bit-wise.
- Adds a new test for Select, where mask is non-canonical (not 0's and -1's).

LOG=N
BUG=v8:6020

Review-Url: https://codereview.chromium.org/2919203002
Cr-Commit-Position: refs/heads/master@{#45795}
This commit is contained in:
bbudge 2017-06-08 13:54:32 -07:00 committed by Commit Bot
parent af76779aa3
commit 381f7da02c
38 changed files with 193 additions and 884 deletions
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7
src/compiler/arm/code-generator-arm.cc
View File

@ -2148,10 +2148,9 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kArmS128Select: {
// vbsl clobbers the mask input so make sure it was DefineSameAsFirst.
DCHECK(i.OutputSimd128Register().is(i.InputSimd128Register(0)));
__ vbsl(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(2));
Simd128Register dst = i.OutputSimd128Register();
DCHECK(dst.is(i.InputSimd128Register(0)));
__ vbsl(dst, i.InputSimd128Register(1), i.InputSimd128Register(2));
break;
}
case kArmS32x4ZipLeft: {

72
src/compiler/arm/instruction-selector-arm.cc
View File

@ -112,15 +112,6 @@ void VisitRRRShuffle(InstructionSelector* selector, ArchOpcode opcode,
g.UseRegister(node->InputAt(1)));
}
void VisitRRRR(InstructionSelector* selector, ArchOpcode opcode, Node* node) {
ArmOperandGenerator g(selector);
// Use DefineSameAsFirst for ternary ops that clobber their first input,
// e.g. the NEON vbsl instruction.
selector->Emit(
opcode, g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(1)), g.UseRegister(node->InputAt(2)));
}
void VisitRRI(InstructionSelector* selector, ArchOpcode opcode, Node* node) {
ArmOperandGenerator g(selector);
int32_t imm = OpParameter<int32_t>(node);
@ -459,9 +450,6 @@ void InstructionSelector::VisitLoad(Node* node) {
opcode = kArmVld1S128;
break;
case MachineRepresentation::kWord64: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -549,9 +537,6 @@ void InstructionSelector::VisitStore(Node* node) {
opcode = kArmVst1S128;
break;
case MachineRepresentation::kWord64: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -758,9 +743,6 @@ void InstructionSelector::VisitCheckedLoad(Node* node) {
case MachineRepresentation::kTagged: // Fall through.
case MachineRepresentation::kWord64: // Fall through.
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -805,9 +787,6 @@ void InstructionSelector::VisitCheckedStore(Node* node) {
case MachineRepresentation::kTagged: // Fall through.
case MachineRepresentation::kWord64: // Fall through.
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -2390,15 +2369,9 @@ VISIT_ATOMIC_BINOP(Xor)
V(I8x16)
#define SIMD_FORMAT_LIST(V) \
V(32x4) \
V(16x8) \
V(8x16)
#define SIMD_ZERO_OP_LIST(V) \
V(S128Zero) \
V(S1x4Zero) \
V(S1x8Zero) \
V(S1x16Zero)
V(32x4, 4) \
V(16x8, 8) \
V(8x16, 16)
#define SIMD_UNOP_LIST(V) \
V(F32x4SConvertI32x4, kArmF32x4SConvertI32x4) \
@ -2421,13 +2394,10 @@ VISIT_ATOMIC_BINOP(Xor)
V(I16x8UConvertI8x16High, kArmI16x8UConvertI8x16High) \
V(I8x16Neg, kArmI8x16Neg) \
V(S128Not, kArmS128Not) \
V(S1x4Not, kArmS128Not) \
V(S1x4AnyTrue, kArmS1x4AnyTrue) \
V(S1x4AllTrue, kArmS1x4AllTrue) \
V(S1x8Not, kArmS128Not) \
V(S1x8AnyTrue, kArmS1x8AnyTrue) \
V(S1x8AllTrue, kArmS1x8AllTrue) \
V(S1x16Not, kArmS128Not) \
V(S1x16AnyTrue, kArmS1x16AnyTrue) \
V(S1x16AllTrue, kArmS1x16AllTrue)
@ -2508,16 +2478,12 @@ VISIT_ATOMIC_BINOP(Xor)
V(I8x16GeU, kArmI8x16GeU) \
V(S128And, kArmS128And) \
V(S128Or, kArmS128Or) \
V(S128Xor, kArmS128Xor) \
V(S1x4And, kArmS128And) \
V(S1x4Or, kArmS128Or) \
V(S1x4Xor, kArmS128Xor) \
V(S1x8And, kArmS128And) \
V(S1x8Or, kArmS128Or) \
V(S1x8Xor, kArmS128Xor) \
V(S1x16And, kArmS128And) \
V(S1x16Or, kArmS128Or) \
V(S1x16Xor, kArmS128Xor)
V(S128Xor, kArmS128Xor)
void InstructionSelector::VisitS128Zero(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmS128Zero, g.DefineAsRegister(node), g.DefineAsRegister(node));
}
#define SIMD_VISIT_SPLAT(Type) \
void InstructionSelector::Visit##Type##Splat(Node* node) { \
@ -2540,14 +2506,6 @@ SIMD_TYPE_LIST(SIMD_VISIT_EXTRACT_LANE)
SIMD_TYPE_LIST(SIMD_VISIT_REPLACE_LANE)
#undef SIMD_VISIT_REPLACE_LANE
#define SIMD_VISIT_ZERO_OP(Name) \
void InstructionSelector::Visit##Name(Node* node) { \
ArmOperandGenerator g(this); \
Emit(kArmS128Zero, g.DefineAsRegister(node), g.DefineAsRegister(node)); \
}
SIMD_ZERO_OP_LIST(SIMD_VISIT_ZERO_OP)
#undef SIMD_VISIT_ZERO_OP
#define SIMD_VISIT_UNOP(Name, instruction) \
void InstructionSelector::Visit##Name(Node* node) { \
VisitRR(this, instruction, node); \
@ -2569,12 +2527,12 @@ SIMD_SHIFT_OP_LIST(SIMD_VISIT_SHIFT_OP)
SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
#undef SIMD_VISIT_BINOP
#define SIMD_VISIT_SELECT_OP(format) \
void InstructionSelector::VisitS##format##Select(Node* node) { \
VisitRRRR(this, kArmS128Select, node); \
}
SIMD_FORMAT_LIST(SIMD_VISIT_SELECT_OP)
#undef SIMD_VISIT_SELECT_OP
void InstructionSelector::VisitS128Select(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmS128Select, g.DefineSameAsFirst(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)),
g.UseRegister(node->InputAt(2)));
}
namespace {
template <int LANES>

12
src/compiler/arm64/instruction-selector-arm64.cc
View File

@ -602,9 +602,6 @@ void InstructionSelector::VisitLoad(Node* node) {
immediate_mode = kLoadStoreImm64;
break;
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -701,9 +698,6 @@ void InstructionSelector::VisitStore(Node* node) {
immediate_mode = kLoadStoreImm64;
break;
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -772,9 +766,6 @@ void InstructionSelector::VisitCheckedLoad(Node* node) {
case MachineRepresentation::kTaggedPointer: // Fall through.
case MachineRepresentation::kTagged: // Fall through.
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -827,9 +818,6 @@ void InstructionSelector::VisitCheckedStore(Node* node) {
case MachineRepresentation::kTaggedPointer: // Fall through.
case MachineRepresentation::kTagged: // Fall through.
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;

12
src/compiler/ia32/instruction-selector-ia32.cc
View File

@ -247,9 +247,6 @@ void InstructionSelector::VisitLoad(Node* node) {
break;
case MachineRepresentation::kWord64: // Fall through.
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -340,9 +337,6 @@ void InstructionSelector::VisitStore(Node* node) {
break;
case MachineRepresentation::kWord64: // Fall through.
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -410,9 +404,6 @@ void InstructionSelector::VisitCheckedLoad(Node* node) {
case MachineRepresentation::kTagged: // Fall through.
case MachineRepresentation::kWord64: // Fall through.
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -486,9 +477,6 @@ void InstructionSelector::VisitCheckedStore(Node* node) {
case MachineRepresentation::kTagged: // Fall through.
case MachineRepresentation::kWord64: // Fall through.
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;

127
src/compiler/instruction-selector.cc
View File

@ -1524,13 +1524,13 @@ void InstructionSelector::VisitNode(Node* node) {
case IrOpcode::kF32x4Max:
return MarkAsSimd128(node), VisitF32x4Max(node);
case IrOpcode::kF32x4Eq:
return MarkAsSimd1x4(node), VisitF32x4Eq(node);
return MarkAsSimd128(node), VisitF32x4Eq(node);
case IrOpcode::kF32x4Ne:
return MarkAsSimd1x4(node), VisitF32x4Ne(node);
return MarkAsSimd128(node), VisitF32x4Ne(node);
case IrOpcode::kF32x4Lt:
return MarkAsSimd1x4(node), VisitF32x4Lt(node);
return MarkAsSimd128(node), VisitF32x4Lt(node);
case IrOpcode::kF32x4Le:
return MarkAsSimd1x4(node), VisitF32x4Le(node);
return MarkAsSimd128(node), VisitF32x4Le(node);
case IrOpcode::kI32x4Splat:
return MarkAsSimd128(node), VisitI32x4Splat(node);
case IrOpcode::kI32x4ExtractLane:
@ -1562,13 +1562,13 @@ void InstructionSelector::VisitNode(Node* node) {
case IrOpcode::kI32x4MaxS:
return MarkAsSimd128(node), VisitI32x4MaxS(node);
case IrOpcode::kI32x4Eq:
return MarkAsSimd1x4(node), VisitI32x4Eq(node);
return MarkAsSimd128(node), VisitI32x4Eq(node);
case IrOpcode::kI32x4Ne:
return MarkAsSimd1x4(node), VisitI32x4Ne(node);
return MarkAsSimd128(node), VisitI32x4Ne(node);
case IrOpcode::kI32x4GtS:
return MarkAsSimd1x4(node), VisitI32x4GtS(node);
return MarkAsSimd128(node), VisitI32x4GtS(node);
case IrOpcode::kI32x4GeS:
return MarkAsSimd1x4(node), VisitI32x4GeS(node);
return MarkAsSimd128(node), VisitI32x4GeS(node);
case IrOpcode::kI32x4UConvertF32x4:
return MarkAsSimd128(node), VisitI32x4UConvertF32x4(node);
case IrOpcode::kI32x4UConvertI16x8Low:
@ -1582,9 +1582,9 @@ void InstructionSelector::VisitNode(Node* node) {
case IrOpcode::kI32x4MaxU:
return MarkAsSimd128(node), VisitI32x4MaxU(node);
case IrOpcode::kI32x4GtU:
return MarkAsSimd1x4(node), VisitI32x4GtU(node);
return MarkAsSimd128(node), VisitI32x4GtU(node);
case IrOpcode::kI32x4GeU:
return MarkAsSimd1x4(node), VisitI32x4GeU(node);
return MarkAsSimd128(node), VisitI32x4GeU(node);
case IrOpcode::kI16x8Splat:
return MarkAsSimd128(node), VisitI16x8Splat(node);
case IrOpcode::kI16x8ExtractLane:
@ -1620,13 +1620,13 @@ void InstructionSelector::VisitNode(Node* node) {
case IrOpcode::kI16x8MaxS:
return MarkAsSimd128(node), VisitI16x8MaxS(node);
case IrOpcode::kI16x8Eq:
return MarkAsSimd1x8(node), VisitI16x8Eq(node);
return MarkAsSimd128(node), VisitI16x8Eq(node);
case IrOpcode::kI16x8Ne:
return MarkAsSimd1x8(node), VisitI16x8Ne(node);
return MarkAsSimd128(node), VisitI16x8Ne(node);
case IrOpcode::kI16x8GtS:
return MarkAsSimd1x8(node), VisitI16x8GtS(node);
return MarkAsSimd128(node), VisitI16x8GtS(node);
case IrOpcode::kI16x8GeS:
return MarkAsSimd1x8(node), VisitI16x8GeS(node);
return MarkAsSimd128(node), VisitI16x8GeS(node);
case IrOpcode::kI16x8UConvertI8x16Low:
return MarkAsSimd128(node), VisitI16x8UConvertI8x16Low(node);
case IrOpcode::kI16x8UConvertI8x16High:
@ -1644,9 +1644,9 @@ void InstructionSelector::VisitNode(Node* node) {
case IrOpcode::kI16x8MaxU:
return MarkAsSimd128(node), VisitI16x8MaxU(node);
case IrOpcode::kI16x8GtU:
return MarkAsSimd1x8(node), VisitI16x8GtU(node);
return MarkAsSimd128(node), VisitI16x8GtU(node);
case IrOpcode::kI16x8GeU:
return MarkAsSimd1x8(node), VisitI16x8GeU(node);
return MarkAsSimd128(node), VisitI16x8GeU(node);
case IrOpcode::kI8x16Splat:
return MarkAsSimd128(node), VisitI8x16Splat(node);
case IrOpcode::kI8x16ExtractLane:
@ -1676,13 +1676,13 @@ void InstructionSelector::VisitNode(Node* node) {
case IrOpcode::kI8x16MaxS:
return MarkAsSimd128(node), VisitI8x16MaxS(node);
case IrOpcode::kI8x16Eq:
return MarkAsSimd1x16(node), VisitI8x16Eq(node);
return MarkAsSimd128(node), VisitI8x16Eq(node);
case IrOpcode::kI8x16Ne:
return MarkAsSimd1x16(node), VisitI8x16Ne(node);
return MarkAsSimd128(node), VisitI8x16Ne(node);
case IrOpcode::kI8x16GtS:
return MarkAsSimd1x16(node), VisitI8x16GtS(node);
return MarkAsSimd128(node), VisitI8x16GtS(node);
case IrOpcode::kI8x16GeS:
return MarkAsSimd1x16(node), VisitI8x16GeS(node);
return MarkAsSimd128(node), VisitI8x16GeS(node);
case IrOpcode::kI8x16ShrU:
return MarkAsSimd128(node), VisitI8x16ShrU(node);
case IrOpcode::kI8x16UConvertI16x8:
@ -1696,9 +1696,9 @@ void InstructionSelector::VisitNode(Node* node) {
case IrOpcode::kI8x16MaxU:
return MarkAsSimd128(node), VisitI8x16MaxU(node);
case IrOpcode::kI8x16GtU:
return MarkAsSimd1x16(node), VisitI8x16GtU(node);
return MarkAsSimd128(node), VisitI8x16GtU(node);
case IrOpcode::kI8x16GeU:
return MarkAsSimd1x16(node), VisitI16x8GeU(node);
return MarkAsSimd128(node), VisitI16x8GeU(node);
case IrOpcode::kS128Zero:
return MarkAsSimd128(node), VisitS128Zero(node);
case IrOpcode::kS128And:
@ -1709,56 +1709,22 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsSimd128(node), VisitS128Xor(node);
case IrOpcode::kS128Not:
return MarkAsSimd128(node), VisitS128Not(node);
case IrOpcode::kS128Select:
return MarkAsSimd128(node), VisitS128Select(node);
case IrOpcode::kS32x4Shuffle:
return MarkAsSimd128(node), VisitS32x4Shuffle(node);
case IrOpcode::kS32x4Select:
return MarkAsSimd128(node), VisitS32x4Select(node);
case IrOpcode::kS16x8Shuffle:
return MarkAsSimd128(node), VisitS16x8Shuffle(node);
case IrOpcode::kS16x8Select:
return MarkAsSimd128(node), VisitS16x8Select(node);
case IrOpcode::kS8x16Shuffle:
return MarkAsSimd128(node), VisitS8x16Shuffle(node);
case IrOpcode::kS8x16Select:
return MarkAsSimd128(node), VisitS8x16Select(node);
case IrOpcode::kS1x4Zero:
return MarkAsSimd1x4(node), VisitS1x4Zero(node);
case IrOpcode::kS1x4And:
return MarkAsSimd1x4(node), VisitS1x4And(node);
case IrOpcode::kS1x4Or:
return MarkAsSimd1x4(node), VisitS1x4Or(node);
case IrOpcode::kS1x4Xor:
return MarkAsSimd1x4(node), VisitS1x4Xor(node);
case IrOpcode::kS1x4Not:
return MarkAsSimd1x4(node), VisitS1x4Not(node);
case IrOpcode::kS1x4AnyTrue:
return MarkAsWord32(node), VisitS1x4AnyTrue(node);
case IrOpcode::kS1x4AllTrue:
return MarkAsWord32(node), VisitS1x4AllTrue(node);
case IrOpcode::kS1x8Zero:
return MarkAsSimd1x8(node), VisitS1x8Zero(node);
case IrOpcode::kS1x8And:
return MarkAsSimd1x8(node), VisitS1x8And(node);
case IrOpcode::kS1x8Or:
return MarkAsSimd1x8(node), VisitS1x8Or(node);
case IrOpcode::kS1x8Xor:
return MarkAsSimd1x8(node), VisitS1x8Xor(node);
case IrOpcode::kS1x8Not:
return MarkAsSimd1x8(node), VisitS1x8Not(node);
case IrOpcode::kS1x8AnyTrue:
return MarkAsWord32(node), VisitS1x8AnyTrue(node);
case IrOpcode::kS1x8AllTrue:
return MarkAsWord32(node), VisitS1x8AllTrue(node);
case IrOpcode::kS1x16Zero:
return MarkAsSimd1x16(node), VisitS1x16Zero(node);
case IrOpcode::kS1x16And:
return MarkAsSimd1x16(node), VisitS1x16And(node);
case IrOpcode::kS1x16Or:
return MarkAsSimd1x16(node), VisitS1x16Or(node);
case IrOpcode::kS1x16Xor:
return MarkAsSimd1x16(node), VisitS1x16Xor(node);
case IrOpcode::kS1x16Not:
return MarkAsSimd1x16(node), VisitS1x16Not(node);
case IrOpcode::kS1x16AnyTrue:
return MarkAsWord32(node), VisitS1x16AnyTrue(node);
case IrOpcode::kS1x16AllTrue:
@ -2412,18 +2378,12 @@ void InstructionSelector::VisitS128Not(Node* node) { UNIMPLEMENTED(); }
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && \
!V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitS128Zero(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x4Zero(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x8Zero(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x16Zero(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS &&
// !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && \
!V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitS32x4Select(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS128Select(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS &&
// !V8_TARGET_ARCH_MIPS64
@ -2434,56 +2394,19 @@ void InstructionSelector::VisitS16x8Shuffle(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && \
!V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitS16x8Select(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS &&
// !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_ARM
void InstructionSelector::VisitS8x16Shuffle(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM
#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && \
!V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitS8x16Select(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS &&
// !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitS1x4And(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x4Or(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x4Xor(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x4Not(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x4AnyTrue(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x4AllTrue(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x8And(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x8Or(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x8Xor(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x8Not(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x8AnyTrue(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x8AllTrue(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x16And(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x16Or(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x16Xor(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x16Not(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x16AnyTrue(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitS1x16AllTrue(Node* node) { UNIMPLEMENTED(); }

21
src/compiler/instruction-selector.h
View File

@ -263,27 +263,6 @@ class V8_EXPORT_PRIVATE InstructionSelector final {
void MarkAsSimd128(Node* node) {
MarkAsRepresentation(MachineRepresentation::kSimd128, node);
}
void MarkAsSimd1x4(Node* node) {
if (kSimdMaskRegisters) {
MarkAsRepresentation(MachineRepresentation::kSimd1x4, node);
} else {
MarkAsSimd128(node);
}
}
void MarkAsSimd1x8(Node* node) {
if (kSimdMaskRegisters) {
MarkAsRepresentation(MachineRepresentation::kSimd1x8, node);
} else {
MarkAsSimd128(node);
}
}
void MarkAsSimd1x16(Node* node) {
if (kSimdMaskRegisters) {
MarkAsRepresentation(MachineRepresentation::kSimd1x16, node);
} else {
MarkAsSimd128(node);
}
}
void MarkAsReference(Node* node) {
MarkAsRepresentation(MachineRepresentation::kTagged, node);
}

18
src/compiler/instruction.cc
View File

@ -209,15 +209,6 @@ std::ostream& operator<<(std::ostream& os,
case MachineRepresentation::kSimd128:
os << "|s128";
break;
case MachineRepresentation::kSimd1x4:
os << "|s1x4";
break;
case MachineRepresentation::kSimd1x8:
os << "|s1x8";
break;
case MachineRepresentation::kSimd1x16:
os << "|s1x16";
break;
case MachineRepresentation::kTaggedSigned:
os << "|ts";
break;
@ -889,15 +880,12 @@ static MachineRepresentation FilterRepresentation(MachineRepresentation rep) {
return InstructionSequence::DefaultRepresentation();
case MachineRepresentation::kWord32:
case MachineRepresentation::kWord64:
case MachineRepresentation::kFloat32:
case MachineRepresentation::kFloat64:
case MachineRepresentation::kSimd128:
case MachineRepresentation::kSimd1x4:
case MachineRepresentation::kSimd1x8:
case MachineRepresentation::kSimd1x16:
case MachineRepresentation::kTaggedSigned:
case MachineRepresentation::kTaggedPointer:
case MachineRepresentation::kTagged:
case MachineRepresentation::kFloat32:
case MachineRepresentation::kFloat64:
case MachineRepresentation::kSimd128:
return rep;
case MachineRepresentation::kNone:
break;

8
src/compiler/instruction.h
View File

@ -479,9 +479,6 @@ class LocationOperand : public InstructionOperand {
case MachineRepresentation::kFloat32:
case MachineRepresentation::kFloat64:
case MachineRepresentation::kSimd128:
case MachineRepresentation::kSimd1x4:
case MachineRepresentation::kSimd1x8:
case MachineRepresentation::kSimd1x16:
case MachineRepresentation::kTaggedSigned:
case MachineRepresentation::kTaggedPointer:
case MachineRepresentation::kTagged:
@ -590,9 +587,8 @@ bool InstructionOperand::IsDoubleRegister() const {
}
bool InstructionOperand::IsSimd128Register() const {
return IsAnyRegister() &&
LocationOperand::cast(this)->representation() ==
MachineRepresentation::kSimd128;
return IsAnyRegister() && LocationOperand::cast(this)->representation() ==
MachineRepresentation::kSimd128;
}
bool InstructionOperand::IsAnyStackSlot() const {

3
src/compiler/js-native-context-specialization.cc
View File

@ -1805,9 +1805,6 @@ JSNativeContextSpecialization::BuildPropertyAccess(
case MachineRepresentation::kWord64:
case MachineRepresentation::kFloat32:
case MachineRepresentation::kSimd128:
case MachineRepresentation::kSimd1x4:
case MachineRepresentation::kSimd1x8:
case MachineRepresentation::kSimd1x16:
UNREACHABLE();
break;
}

9
src/compiler/load-elimination.cc
View File

@ -819,9 +819,6 @@ Reduction LoadElimination::ReduceLoadElement(Node* node) {
ElementAccess const& access = ElementAccessOf(node->op());
switch (access.machine_type.representation()) {
case MachineRepresentation::kNone:
case MachineRepresentation::kSimd1x4:
case MachineRepresentation::kSimd1x8:
case MachineRepresentation::kSimd1x16:
case MachineRepresentation::kBit:
UNREACHABLE();
break;
@ -879,9 +876,6 @@ Reduction LoadElimination::ReduceStoreElement(Node* node) {
// Only record the new value if the store doesn't have an implicit truncation.
switch (access.machine_type.representation()) {
case MachineRepresentation::kNone:
case MachineRepresentation::kSimd1x4:
case MachineRepresentation::kSimd1x8:
case MachineRepresentation::kSimd1x16:
case MachineRepresentation::kBit:
UNREACHABLE();
break;
@ -1092,9 +1086,6 @@ int LoadElimination::FieldIndexOf(FieldAccess const& access) {
case MachineRepresentation::kNone:
case MachineRepresentation::kBit:
case MachineRepresentation::kSimd128:
case MachineRepresentation::kSimd1x4:
case MachineRepresentation::kSimd1x8:
case MachineRepresentation::kSimd1x16:
UNREACHABLE();
break;
case MachineRepresentation::kWord32:

3
src/compiler/machine-graph-verifier.cc
View File

@ -794,9 +794,6 @@ class MachineRepresentationChecker {
case MachineRepresentation::kFloat32:
case MachineRepresentation::kFloat64:
case MachineRepresentation::kSimd128:
case MachineRepresentation::kSimd1x4:
case MachineRepresentation::kSimd1x8:
case MachineRepresentation::kSimd1x16:
case MachineRepresentation::kBit:
case MachineRepresentation::kWord8:
case MachineRepresentation::kWord16:

31
src/compiler/machine-operator.cc
View File

@ -333,28 +333,11 @@ MachineType AtomicOpRepresentationOf(Operator const* op) {
V(S128Or, Operator::kAssociative | Operator::kCommutative, 2, 0, 1) \
V(S128Xor, Operator::kAssociative | Operator::kCommutative, 2, 0, 1) \
V(S128Not, Operator::kNoProperties, 1, 0, 1) \
V(S32x4Select, Operator::kNoProperties, 3, 0, 1) \
V(S16x8Select, Operator::kNoProperties, 3, 0, 1) \
V(S8x16Select, Operator::kNoProperties, 3, 0, 1) \
V(S1x4Zero, Operator::kNoProperties, 0, 0, 1) \
V(S1x4And, Operator::kAssociative | Operator::kCommutative, 2, 0, 1) \
V(S1x4Or, Operator::kAssociative | Operator::kCommutative, 2, 0, 1) \
V(S1x4Xor, Operator::kAssociative | Operator::kCommutative, 2, 0, 1) \
V(S1x4Not, Operator::kNoProperties, 1, 0, 1) \
V(S128Select, Operator::kNoProperties, 3, 0, 1) \
V(S1x4AnyTrue, Operator::kNoProperties, 1, 0, 1) \
V(S1x4AllTrue, Operator::kNoProperties, 1, 0, 1) \
V(S1x8Zero, Operator::kNoProperties, 0, 0, 1) \
V(S1x8And, Operator::kAssociative | Operator::kCommutative, 2, 0, 1) \
V(S1x8Or, Operator::kAssociative | Operator::kCommutative, 2, 0, 1) \
V(S1x8Xor, Operator::kAssociative | Operator::kCommutative, 2, 0, 1) \
V(S1x8Not, Operator::kNoProperties, 1, 0, 1) \
V(S1x8AnyTrue, Operator::kNoProperties, 1, 0, 1) \
V(S1x8AllTrue, Operator::kNoProperties, 1, 0, 1) \
V(S1x16Zero, Operator::kNoProperties, 0, 0, 1) \
V(S1x16And, Operator::kAssociative | Operator::kCommutative, 2, 0, 1) \
V(S1x16Or, Operator::kAssociative | Operator::kCommutative, 2, 0, 1) \
V(S1x16Xor, Operator::kAssociative | Operator::kCommutative, 2, 0, 1) \
V(S1x16Not, Operator::kNoProperties, 1, 0, 1) \
V(S1x16AnyTrue, Operator::kNoProperties, 1, 0, 1) \
V(S1x16AllTrue, Operator::kNoProperties, 1, 0, 1)
@ -721,9 +704,6 @@ const Operator* MachineOperatorBuilder::UnalignedStore(
MACHINE_REPRESENTATION_LIST(STORE)
#undef STORE
case MachineRepresentation::kBit:
case MachineRepresentation::kSimd1x4:
case MachineRepresentation::kSimd1x8:
case MachineRepresentation::kSimd1x16:
case MachineRepresentation::kNone:
break;
}
@ -806,9 +786,6 @@ const Operator* MachineOperatorBuilder::Store(StoreRepresentation store_rep) {
MACHINE_REPRESENTATION_LIST(STORE)
#undef STORE
case MachineRepresentation::kBit:
case MachineRepresentation::kSimd1x4:
case MachineRepresentation::kSimd1x8:
case MachineRepresentation::kSimd1x16:
case MachineRepresentation::kNone:
break;
}
@ -825,9 +802,6 @@ const Operator* MachineOperatorBuilder::ProtectedStore(
MACHINE_REPRESENTATION_LIST(STORE)
#undef STORE
case MachineRepresentation::kBit:
case MachineRepresentation::kSimd1x4:
case MachineRepresentation::kSimd1x8:
case MachineRepresentation::kSimd1x16:
case MachineRepresentation::kNone:
break;
}
@ -871,9 +845,6 @@ const Operator* MachineOperatorBuilder::CheckedStore(
MACHINE_REPRESENTATION_LIST(STORE)
#undef STORE
case MachineRepresentation::kBit:
case MachineRepresentation::kSimd1x4:
case MachineRepresentation::kSimd1x8:
case MachineRepresentation::kSimd1x16:
case MachineRepresentation::kNone:
break;
}

21
src/compiler/machine-operator.h
View File

@ -575,35 +575,16 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* S128Or();
const Operator* S128Xor();
const Operator* S128Not();
const Operator* S128Select();
const Operator* S32x4Shuffle(uint8_t shuffle[16]);
const Operator* S32x4Select();
const Operator* S16x8Shuffle(uint8_t shuffle[16]);
const Operator* S16x8Select();
const Operator* S8x16Shuffle(uint8_t shuffle[16]);
const Operator* S8x16Select();
const Operator* S1x4Zero();
const Operator* S1x4And();
const Operator* S1x4Or();
const Operator* S1x4Xor();
const Operator* S1x4Not();
const Operator* S1x4AnyTrue();
const Operator* S1x4AllTrue();
const Operator* S1x8Zero();
const Operator* S1x8And();
const Operator* S1x8Or();
const Operator* S1x8Xor();
const Operator* S1x8Not();
const Operator* S1x8AnyTrue();
const Operator* S1x8AllTrue();
const Operator* S1x16Zero();
const Operator* S1x16And();
const Operator* S1x16Or();
const Operator* S1x16Xor();
const Operator* S1x16Not();
const Operator* S1x16AnyTrue();
const Operator* S1x16AllTrue();

4
src/compiler/mips/code-generator-mips.cc
View File

@ -1780,9 +1780,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1));
break;
}
case kMipsS32x4Select:
case kMipsS16x8Select:
case kMipsS8x16Select: {
case kMipsS128Select: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
DCHECK(i.OutputSimd128Register().is(i.InputSimd128Register(0)));
__ bsel_v(i.OutputSimd128Register(), i.InputSimd128Register(2),

4
src/compiler/mips/instruction-codes-mips.h
View File

@ -154,7 +154,6 @@ namespace compiler {
V(MipsI32x4ShrU) \
V(MipsI32x4MaxU) \
V(MipsI32x4MinU) \
V(MipsS32x4Select) \
V(MipsF32x4Abs) \
V(MipsF32x4Neg) \
V(MipsF32x4RecipApprox) \
@ -205,8 +204,6 @@ namespace compiler {
V(MipsI8x16Neg) \
V(MipsI8x16Shl) \
V(MipsI8x16ShrS) \
V(MipsS16x8Select) \
V(MipsS8x16Select) \
V(MipsI8x16Add) \
V(MipsI8x16AddSaturateS) \
V(MipsI8x16Sub) \
@ -229,6 +226,7 @@ namespace compiler {
V(MipsS128Or) \
V(MipsS128Xor) \
V(MipsS128Not) \
V(MipsS128Select) \
V(MipsS1x4AnyTrue) \
V(MipsS1x4AllTrue) \
V(MipsS1x8AnyTrue) \

55
src/compiler/mips/instruction-selector-mips.cc
View File

@ -298,9 +298,6 @@ void InstructionSelector::VisitLoad(Node* node) {
opcode = kMipsMsaLd;
break;
case MachineRepresentation::kWord64: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -388,9 +385,6 @@ void InstructionSelector::VisitStore(Node* node) {
opcode = kMipsMsaSt;
break;
case MachineRepresentation::kWord64: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -1242,9 +1236,6 @@ void InstructionSelector::VisitUnalignedLoad(Node* node) {
opcode = kMipsMsaLd;
break;
case MachineRepresentation::kWord64: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -1297,9 +1288,6 @@ void InstructionSelector::VisitUnalignedStore(Node* node) {
opcode = kMipsMsaSt;
break;
case MachineRepresentation::kWord64: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -1348,9 +1336,6 @@ void InstructionSelector::VisitCheckedLoad(Node* node) {
case MachineRepresentation::kTagged: // Fall through.
case MachineRepresentation::kWord64: // Fall through.
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -1960,12 +1945,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(16x8) \
V(8x16)
#define SIMD_ZERO_OP_LIST(V) \
V(S128Zero) \
V(S1x4Zero) \
V(S1x8Zero) \
V(S1x16Zero)
#define SIMD_UNOP_LIST(V) \
V(F32x4SConvertI32x4, kMipsF32x4SConvertI32x4) \
V(F32x4UConvertI32x4, kMipsF32x4UConvertI32x4) \
@ -1979,13 +1958,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I16x8Neg, kMipsI16x8Neg) \
V(I8x16Neg, kMipsI8x16Neg) \
V(S128Not, kMipsS128Not) \
V(S1x4Not, kMipsS128Not) \
V(S1x4AnyTrue, kMipsS1x4AnyTrue) \
V(S1x4AllTrue, kMipsS1x4AllTrue) \
V(S1x8Not, kMipsS128Not) \
V(S1x8AnyTrue, kMipsS1x8AnyTrue) \
V(S1x8AllTrue, kMipsS1x8AllTrue) \
V(S1x16Not, kMipsS128Not) \
V(S1x16AnyTrue, kMipsS1x16AnyTrue) \
V(S1x16AllTrue, kMipsS1x16AllTrue)
@ -2059,24 +2035,12 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16GeU, kMipsI8x16GeU) \
V(S128And, kMipsS128And) \
V(S128Or, kMipsS128Or) \
V(S128Xor, kMipsS128Xor) \
V(S1x4And, kMipsS128And) \
V(S1x4Or, kMipsS128Or) \
V(S1x4Xor, kMipsS128Xor) \
V(S1x8And, kMipsS128And) \
V(S1x8Or, kMipsS128Or) \
V(S1x8Xor, kMipsS128Xor) \
V(S1x16And, kMipsS128And) \
V(S1x16Or, kMipsS128Or) \
V(S1x16Xor, kMipsS128Xor)
V(S128Xor, kMipsS128Xor)
#define SIMD_VISIT_ZERO_OP(Name) \
void InstructionSelector::Visit##Name(Node* node) { \
MipsOperandGenerator g(this); \
Emit(kMipsS128Zero, g.DefineSameAsFirst(node)); \
}
SIMD_ZERO_OP_LIST(SIMD_VISIT_ZERO_OP)
#undef SIMD_VISIT_ZERO_OP
void InstructionSelector::VisitS128Zero(Node* node) {
MipsOperandGenerator g(this);
Emit(kMipsS128Zero, g.DefineSameAsFirst(node));
}
#define SIMD_VISIT_SPLAT(Type) \
void InstructionSelector::Visit##Type##Splat(Node* node) { \
@ -2120,12 +2084,9 @@ SIMD_SHIFT_OP_LIST(SIMD_VISIT_SHIFT_OP)
SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
#undef SIMD_VISIT_BINOP
#define SIMD_VISIT_SELECT_OP(format) \
void InstructionSelector::VisitS##format##Select(Node* node) { \
VisitRRRR(this, kMipsS##format##Select, node); \
}
SIMD_FORMAT_LIST(SIMD_VISIT_SELECT_OP)
#undef SIMD_VISIT_SELECT_OP
void InstructionSelector::VisitS128Select(Node* node) {
VisitRRRR(this, kMipsS128Select, node);
}
// static
MachineOperatorBuilder::Flags

4
src/compiler/mips64/code-generator-mips64.cc
View File

@ -2100,9 +2100,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1));
break;
}
case kMips64S32x4Select:
case kMips64S16x8Select:
case kMips64S8x16Select: {
case kMips64S128Select: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
DCHECK(i.OutputSimd128Register().is(i.InputSimd128Register(0)));
__ bsel_v(i.OutputSimd128Register(), i.InputSimd128Register(2),

4
src/compiler/mips64/instruction-codes-mips64.h
View File

@ -188,7 +188,6 @@ namespace compiler {
V(Mips64I32x4ShrU) \
V(Mips64I32x4MaxU) \
V(Mips64I32x4MinU) \
V(Mips64S32x4Select) \
V(Mips64F32x4Abs) \
V(Mips64F32x4Neg) \
V(Mips64F32x4RecipApprox) \
@ -239,8 +238,6 @@ namespace compiler {
V(Mips64I8x16Neg) \
V(Mips64I8x16Shl) \
V(Mips64I8x16ShrS) \
V(Mips64S16x8Select) \
V(Mips64S8x16Select) \
V(Mips64I8x16Add) \
V(Mips64I8x16AddSaturateS) \
V(Mips64I8x16Sub) \
@ -263,6 +260,7 @@ namespace compiler {
V(Mips64S128Or) \
V(Mips64S128Xor) \
V(Mips64S128Not) \
V(Mips64S128Select) \
V(Mips64S1x4AnyTrue) \
V(Mips64S1x4AllTrue) \
V(Mips64S1x8AnyTrue) \

58
src/compiler/mips64/instruction-selector-mips64.cc
View File

@ -414,9 +414,6 @@ void InstructionSelector::VisitLoad(Node* node) {
case MachineRepresentation::kSimd128:
opcode = kMips64MsaLd;
break;
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -496,9 +493,6 @@ void InstructionSelector::VisitStore(Node* node) {
case MachineRepresentation::kSimd128:
opcode = kMips64MsaSt;
break;
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -1792,9 +1786,6 @@ void InstructionSelector::VisitUnalignedLoad(Node* node) {
case MachineRepresentation::kSimd128:
opcode = kMips64MsaLd;
break;
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -1847,9 +1838,6 @@ void InstructionSelector::VisitUnalignedStore(Node* node) {
case MachineRepresentation::kSimd128:
opcode = kMips64MsaSt;
break;
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -1900,9 +1888,6 @@ void InstructionSelector::VisitCheckedLoad(Node* node) {
case MachineRepresentation::kTaggedPointer: // Fall through.
case MachineRepresentation::kTagged:
case MachineRepresentation::kSimd128:
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -1964,9 +1949,6 @@ void InstructionSelector::VisitCheckedStore(Node* node) {
case MachineRepresentation::kTaggedPointer: // Fall through.
case MachineRepresentation::kTagged:
case MachineRepresentation::kSimd128:
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -2712,12 +2694,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(16x8) \
V(8x16)
#define SIMD_ZERO_OP_LIST(V) \
V(S128Zero) \
V(S1x4Zero) \
V(S1x8Zero) \
V(S1x16Zero)
#define SIMD_UNOP_LIST(V) \
V(F32x4SConvertI32x4, kMips64F32x4SConvertI32x4) \
V(F32x4UConvertI32x4, kMips64F32x4UConvertI32x4) \
@ -2731,13 +2707,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I16x8Neg, kMips64I16x8Neg) \
V(I8x16Neg, kMips64I8x16Neg) \
V(S128Not, kMips64S128Not) \
V(S1x4Not, kMips64S128Not) \
V(S1x4AnyTrue, kMips64S1x4AnyTrue) \
V(S1x4AllTrue, kMips64S1x4AllTrue) \
V(S1x8Not, kMips64S128Not) \
V(S1x8AnyTrue, kMips64S1x8AnyTrue) \
V(S1x8AllTrue, kMips64S1x8AllTrue) \
V(S1x16Not, kMips64S128Not) \
V(S1x16AnyTrue, kMips64S1x16AnyTrue) \
V(S1x16AllTrue, kMips64S1x16AllTrue)
@ -2811,24 +2784,12 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16GeU, kMips64I8x16GeU) \
V(S128And, kMips64S128And) \
V(S128Or, kMips64S128Or) \
V(S128Xor, kMips64S128Xor) \
V(S1x4And, kMips64S128And) \
V(S1x4Or, kMips64S128Or) \
V(S1x4Xor, kMips64S128Xor) \
V(S1x8And, kMips64S128And) \
V(S1x8Or, kMips64S128Or) \
V(S1x8Xor, kMips64S128Xor) \
V(S1x16And, kMips64S128And) \
V(S1x16Or, kMips64S128Or) \
V(S1x16Xor, kMips64S128Xor)
V(S128Xor, kMips64S128Xor)
#define SIMD_VISIT_ZERO_OP(Name) \
void InstructionSelector::Visit##Name(Node* node) { \
Mips64OperandGenerator g(this); \
Emit(kMips64S128Zero, g.DefineSameAsFirst(node)); \
}
SIMD_ZERO_OP_LIST(SIMD_VISIT_ZERO_OP)
#undef SIMD_VISIT_ZERO_OP
void InstructionSelector::VisitS128Zero(Node* node) {
Mips64OperandGenerator g(this);
Emit(kMips64S128Zero, g.DefineSameAsFirst(node));
}
#define SIMD_VISIT_SPLAT(Type) \
void InstructionSelector::Visit##Type##Splat(Node* node) { \
@ -2872,12 +2833,9 @@ SIMD_SHIFT_OP_LIST(SIMD_VISIT_SHIFT_OP)
SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
#undef SIMD_VISIT_BINOP
#define SIMD_VISIT_SELECT_OP(format) \
void InstructionSelector::VisitS##format##Select(Node* node) { \
VisitRRRR(this, kMips64S##format##Select, node); \
}
SIMD_FORMAT_LIST(SIMD_VISIT_SELECT_OP)
#undef SIMD_VISIT_SELECT_OP
void InstructionSelector::VisitS128Select(Node* node) {
VisitRRRR(this, kMips64S128Select, node);
}
// static
MachineOperatorBuilder::Flags

19
src/compiler/opcodes.h
View File

@ -699,31 +699,14 @@
V(S128And) \
V(S128Or) \
V(S128Xor) \
V(S128Select) \
V(S32x4Shuffle) \
V(S32x4Select) \
V(S16x8Shuffle) \
V(S16x8Select) \
V(S8x16Shuffle) \
V(S8x16Select) \
V(S1x4Zero) \
V(S1x4And) \
V(S1x4Or) \
V(S1x4Xor) \
V(S1x4Not) \
V(S1x4AnyTrue) \
V(S1x4AllTrue) \
V(S1x8Zero) \
V(S1x8And) \
V(S1x8Or) \
V(S1x8Xor) \
V(S1x8Not) \
V(S1x8AnyTrue) \
V(S1x8AllTrue) \
V(S1x16Zero) \
V(S1x16And) \
V(S1x16Or) \
V(S1x16Xor) \
V(S1x16Not) \
V(S1x16AnyTrue) \
V(S1x16AllTrue)

12
src/compiler/ppc/instruction-selector-ppc.cc
View File

@ -224,9 +224,6 @@ void InstructionSelector::VisitLoad(Node* node) {
case MachineRepresentation::kWord64: // Fall through.
#endif
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -336,9 +333,6 @@ void InstructionSelector::VisitStore(Node* node) {
case MachineRepresentation::kWord64: // Fall through.
#endif
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -403,9 +397,6 @@ void InstructionSelector::VisitCheckedLoad(Node* node) {
case MachineRepresentation::kWord64: // Fall through.
#endif
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -454,9 +445,6 @@ void InstructionSelector::VisitCheckedStore(Node* node) {
case MachineRepresentation::kWord64: // Fall through.
#endif
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;

4
src/compiler/register-allocator.cc
View File

@ -88,10 +88,6 @@ int GetByteWidth(MachineRepresentation rep) {
return kDoubleSize;
case MachineRepresentation::kSimd128:
return kSimd128Size;
case MachineRepresentation::kSimd1x4:
case MachineRepresentation::kSimd1x8:
case MachineRepresentation::kSimd1x16:
return kSimdMaskRegisters ? kPointerSize : kSimd128Size;
case MachineRepresentation::kNone:
break;
}

3
src/compiler/representation-change.cc
View File

@ -194,9 +194,6 @@ Node* RepresentationChanger::GetRepresentationFor(
DCHECK(use_info.type_check() == TypeCheckKind::kNone);
return GetWord64RepresentationFor(node, output_rep, output_type);
case MachineRepresentation::kSimd128:
case MachineRepresentation::kSimd1x4:
case MachineRepresentation::kSimd1x8:
case MachineRepresentation::kSimd1x16:
case MachineRepresentation::kNone:
return node;
}

12
src/compiler/s390/instruction-selector-s390.cc
View File

@ -307,9 +307,6 @@ ArchOpcode SelectLoadOpcode(Node* node) {
case MachineRepresentation::kWord64: // Fall through.
#endif
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
default:
UNREACHABLE();
@ -820,9 +817,6 @@ void InstructionSelector::VisitStore(Node* node) {
case MachineRepresentation::kWord64: // Fall through.
#endif
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -887,9 +881,6 @@ void InstructionSelector::VisitCheckedLoad(Node* node) {
case MachineRepresentation::kWord64: // Fall through.
#endif
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -937,9 +928,6 @@ void InstructionSelector::VisitCheckedStore(Node* node) {
case MachineRepresentation::kWord64: // Fall through.
#endif
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;

31
src/compiler/simd-scalar-lowering.cc
View File

@ -216,7 +216,7 @@ void SimdScalarLowering::SetLoweredType(Node* node, Node* output) {
}
FOREACH_FLOAT32X4_TO_SIMD1X4OPCODE(CASE_STMT)
FOREACH_INT32X4_TO_SIMD1X4OPCODE(CASE_STMT) {
replacements_[node->id()].type = SimdType::kSimd1x4;
replacements_[node->id()].type = SimdType::kInt32x4;
break;
}
FOREACH_INT16X8_OPCODE(CASE_STMT) {
@ -224,7 +224,7 @@ void SimdScalarLowering::SetLoweredType(Node* node, Node* output) {
break;
}
FOREACH_INT16X8_TO_SIMD1X8OPCODE(CASE_STMT) {
replacements_[node->id()].type = SimdType::kSimd1x8;
replacements_[node->id()].type = SimdType::kInt16x8;
break;
}
FOREACH_INT8X16_OPCODE(CASE_STMT) {
@ -232,7 +232,7 @@ void SimdScalarLowering::SetLoweredType(Node* node, Node* output) {
break;
}
FOREACH_INT8X16_TO_SIMD1X16OPCODE(CASE_STMT) {
replacements_[node->id()].type = SimdType::kSimd1x16;
replacements_[node->id()].type = SimdType::kInt8x16;
break;
}
default: {
@ -249,8 +249,8 @@ void SimdScalarLowering::SetLoweredType(Node* node, Node* output) {
replacements_[node->id()].type = SimdType::kFloat32x4;
break;
}
case IrOpcode::kS32x4Select: {
replacements_[node->id()].type = SimdType::kSimd1x4;
case IrOpcode::kS128Select: {
replacements_[node->id()].type = SimdType::kInt32x4;
break;
}
FOREACH_INT16X8_TO_SIMD1X8OPCODE(CASE_STMT) {
@ -261,10 +261,6 @@ void SimdScalarLowering::SetLoweredType(Node* node, Node* output) {
replacements_[node->id()].type = SimdType::kInt8x16;
break;
}
case IrOpcode::kS16x8Select: {
replacements_[node->id()].type = SimdType::kSimd1x8;
break;
}
default: {
replacements_[node->id()].type = replacements_[output->id()].type;
}
@ -310,12 +306,11 @@ static int GetReturnCountAfterLowering(
int SimdScalarLowering::NumLanes(SimdType type) {
int num_lanes = 0;
if (type == SimdType::kFloat32x4 || type == SimdType::kInt32x4 ||
type == SimdType::kSimd1x4) {
if (type == SimdType::kFloat32x4 || type == SimdType::kInt32x4) {
num_lanes = kNumLanes32;
} else if (type == SimdType::kInt16x8 || type == SimdType::kSimd1x8) {
} else if (type == SimdType::kInt16x8) {
num_lanes = kNumLanes16;
} else if (type == SimdType::kInt8x16 || type == SimdType::kSimd1x16) {
} else if (type == SimdType::kInt8x16) {
num_lanes = kNumLanes8;
} else {
UNREACHABLE();
@ -1104,13 +1099,11 @@ void SimdScalarLowering::LowerNode(Node* node) {
LowerNotEqual(node, SimdType::kInt8x16, machine()->Word32Equal());
break;
}
case IrOpcode::kS32x4Select:
case IrOpcode::kS16x8Select:
case IrOpcode::kS8x16Select: {
case IrOpcode::kS128Select: {
DCHECK(node->InputCount() == 3);
DCHECK(ReplacementType(node->InputAt(0)) == SimdType::kSimd1x4 ||
ReplacementType(node->InputAt(0)) == SimdType::kSimd1x8 ||
ReplacementType(node->InputAt(0)) == SimdType::kSimd1x16);
DCHECK(ReplacementType(node->InputAt(0)) == SimdType::kInt32x4 ||
ReplacementType(node->InputAt(0)) == SimdType::kInt16x8 ||
ReplacementType(node->InputAt(0)) == SimdType::kInt8x16);
Node** boolean_input = GetReplacements(node->InputAt(0));
Node** rep_left = GetReplacementsWithType(node->InputAt(1), rep_type);
Node** rep_right = GetReplacementsWithType(node->InputAt(2), rep_type);

10
src/compiler/simd-scalar-lowering.h
View File

@ -28,15 +28,7 @@ class SimdScalarLowering {
private:
enum class State : uint8_t { kUnvisited, kOnStack, kVisited };
enum class SimdType : uint8_t {
kFloat32x4,
kInt32x4,
kInt16x8,
kInt8x16,
kSimd1x4,
kSimd1x8,
kSimd1x16
};
enum class SimdType : uint8_t { kFloat32x4, kInt32x4, kInt16x8, kInt8x16 };
#if defined(V8_TARGET_BIG_ENDIAN)
static constexpr int kLaneOffsets[16] = {15, 14, 13, 12, 11, 10, 9, 8,

3
src/compiler/simplified-lowering.cc
View File

@ -136,9 +136,6 @@ UseInfo TruncatingUseInfoFromRepresentation(MachineRepresentation rep) {
case MachineRepresentation::kBit:
return UseInfo::Bool();
case MachineRepresentation::kSimd128:
case MachineRepresentation::kSimd1x4:
case MachineRepresentation::kSimd1x8:
case MachineRepresentation::kSimd1x16:
case MachineRepresentation::kNone:
break;
}

58
src/compiler/wasm-compiler.cc
View File

@ -3181,21 +3181,6 @@ Node* WasmGraphBuilder::S128Zero() {
return graph()->NewNode(jsgraph()->machine()->S128Zero());
}
Node* WasmGraphBuilder::S1x4Zero() {
has_simd_ = true;
return graph()->NewNode(jsgraph()->machine()->S1x4Zero());
}
Node* WasmGraphBuilder::S1x8Zero() {
has_simd_ = true;
return graph()->NewNode(jsgraph()->machine()->S1x8Zero());
}
Node* WasmGraphBuilder::S1x16Zero() {
has_simd_ = true;
return graph()->NewNode(jsgraph()->machine()->S1x16Zero());
}
Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
const NodeVector& inputs) {
has_simd_ = true;
@ -3502,56 +3487,17 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
inputs[1]);
case wasm::kExprS128Not:
return graph()->NewNode(jsgraph()->machine()->S128Not(), inputs[0]);
case wasm::kExprS32x4Select:
return graph()->NewNode(jsgraph()->machine()->S32x4Select(), inputs[0],
case wasm::kExprS128Select:
return graph()->NewNode(jsgraph()->machine()->S128Select(), inputs[0],
inputs[1], inputs[2]);
case wasm::kExprS16x8Select:
return graph()->NewNode(jsgraph()->machine()->S16x8Select(), inputs[0],
inputs[1], inputs[2]);
case wasm::kExprS8x16Select:
return graph()->NewNode(jsgraph()->machine()->S8x16Select(), inputs[0],
inputs[1], inputs[2]);
case wasm::kExprS1x4And:
return graph()->NewNode(jsgraph()->machine()->S1x4And(), inputs[0],
inputs[1]);
case wasm::kExprS1x4Or:
return graph()->NewNode(jsgraph()->machine()->S1x4Or(), inputs[0],
inputs[1]);
case wasm::kExprS1x4Xor:
return graph()->NewNode(jsgraph()->machine()->S1x4Xor(), inputs[0],
inputs[1]);
case wasm::kExprS1x4Not:
return graph()->NewNode(jsgraph()->machine()->S1x4Not(), inputs[0]);
case wasm::kExprS1x4AnyTrue:
return graph()->NewNode(jsgraph()->machine()->S1x4AnyTrue(), inputs[0]);
case wasm::kExprS1x4AllTrue:
return graph()->NewNode(jsgraph()->machine()->S1x4AllTrue(), inputs[0]);
case wasm::kExprS1x8And:
return graph()->NewNode(jsgraph()->machine()->S1x8And(), inputs[0],
inputs[1]);
case wasm::kExprS1x8Or:
return graph()->NewNode(jsgraph()->machine()->S1x8Or(), inputs[0],
inputs[1]);
case wasm::kExprS1x8Xor:
return graph()->NewNode(jsgraph()->machine()->S1x8Xor(), inputs[0],
inputs[1]);
case wasm::kExprS1x8Not:
return graph()->NewNode(jsgraph()->machine()->S1x8Not(), inputs[0]);
case wasm::kExprS1x8AnyTrue:
return graph()->NewNode(jsgraph()->machine()->S1x8AnyTrue(), inputs[0]);
case wasm::kExprS1x8AllTrue:
return graph()->NewNode(jsgraph()->machine()->S1x8AllTrue(), inputs[0]);
case wasm::kExprS1x16And:
return graph()->NewNode(jsgraph()->machine()->S1x16And(), inputs[0],
inputs[1]);
case wasm::kExprS1x16Or:
return graph()->NewNode(jsgraph()->machine()->S1x16Or(), inputs[0],
inputs[1]);
case wasm::kExprS1x16Xor:
return graph()->NewNode(jsgraph()->machine()->S1x16Xor(), inputs[0],
inputs[1]);
case wasm::kExprS1x16Not:
return graph()->NewNode(jsgraph()->machine()->S1x16Not(), inputs[0]);
case wasm::kExprS1x16AnyTrue:
return graph()->NewNode(jsgraph()->machine()->S1x16AnyTrue(), inputs[0]);
case wasm::kExprS1x16AllTrue:

46
src/compiler/x64/instruction-selector-x64.cc
View File

@ -233,9 +233,6 @@ ArchOpcode GetLoadOpcode(LoadRepresentation load_rep) {
case MachineRepresentation::kSimd128: // Fall through.
opcode = kX64Movdqu;
break;
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
break;
@ -270,9 +267,6 @@ ArchOpcode GetStoreOpcode(StoreRepresentation store_rep) {
case MachineRepresentation::kSimd128: // Fall through.
return kX64Movdqu;
break;
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
}
@ -432,9 +426,6 @@ void InstructionSelector::VisitCheckedLoad(Node* node) {
break;
case MachineRepresentation::kBit: // Fall through.
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kTaggedSigned: // Fall through.
case MachineRepresentation::kTaggedPointer: // Fall through.
case MachineRepresentation::kTagged: // Fall through.
@ -490,9 +481,6 @@ void InstructionSelector::VisitCheckedStore(Node* node) {
break;
case MachineRepresentation::kBit: // Fall through.
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kTaggedSigned: // Fall through.
case MachineRepresentation::kTaggedPointer: // Fall through.
case MachineRepresentation::kTagged: // Fall through.
@ -2460,12 +2448,6 @@ VISIT_ATOMIC_BINOP(Xor)
V(16x8) \
V(8x16)
#define SIMD_ZERO_OP_LIST(V) \
V(S128Zero) \
V(S1x4Zero) \
V(S1x8Zero) \
V(S1x16Zero)
#define SIMD_BINOP_LIST(V) \
V(I32x4Add) \
V(I32x4AddHoriz) \
@ -2517,6 +2499,11 @@ VISIT_ATOMIC_BINOP(Xor)
V(I16x8ShrS) \
V(I16x8ShrU)
void InstructionSelector::VisitS128Zero(Node* node) {
X64OperandGenerator g(this);
Emit(kX64S128Zero, g.DefineAsRegister(node), g.DefineAsRegister(node));
}
#define VISIT_SIMD_SPLAT(Type) \
void InstructionSelector::Visit##Type##Splat(Node* node) { \
X64OperandGenerator g(this); \
@ -2547,14 +2534,6 @@ SIMD_TYPES(VISIT_SIMD_EXTRACT_LANE)
SIMD_TYPES(VISIT_SIMD_REPLACE_LANE)
#undef VISIT_SIMD_REPLACE_LANE
#define SIMD_VISIT_ZERO_OP(Name) \
void InstructionSelector::Visit##Name(Node* node) { \
X64OperandGenerator g(this); \
Emit(kX64S128Zero, g.DefineAsRegister(node), g.DefineAsRegister(node)); \
}
SIMD_ZERO_OP_LIST(SIMD_VISIT_ZERO_OP)
#undef SIMD_VISIT_ZERO_OP
#define VISIT_SIMD_SHIFT(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
X64OperandGenerator g(this); \
@ -2583,15 +2562,12 @@ SIMD_UNOP_LIST(VISIT_SIMD_UNOP)
SIMD_BINOP_LIST(VISIT_SIMD_BINOP)
#undef VISIT_SIMD_BINOP
#define SIMD_VISIT_SELECT_OP(format) \
void InstructionSelector::VisitS##format##Select(Node* node) { \
X64OperandGenerator g(this); \
Emit(kX64S128Select, g.DefineSameAsFirst(node), \
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)), \
g.UseRegister(node->InputAt(2))); \
}
SIMD_FORMAT_LIST(SIMD_VISIT_SELECT_OP)
#undef SIMD_VISIT_SELECT_OP
void InstructionSelector::VisitS128Select(Node* node) {
X64OperandGenerator g(this);
Emit(kX64S128Select, g.DefineSameAsFirst(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)),
g.UseRegister(node->InputAt(2)));
}
void InstructionSelector::VisitInt32AbsWithOverflow(Node* node) {
UNREACHABLE();

12
src/compiler/x87/instruction-selector-x87.cc
View File

@ -203,9 +203,6 @@ void InstructionSelector::VisitLoad(Node* node) {
break;
case MachineRepresentation::kWord64: // Fall through.
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -296,9 +293,6 @@ void InstructionSelector::VisitStore(Node* node) {
break;
case MachineRepresentation::kWord64: // Fall through.
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -366,9 +360,6 @@ void InstructionSelector::VisitCheckedLoad(Node* node) {
case MachineRepresentation::kTagged: // Fall through.
case MachineRepresentation::kWord64: // Fall through.
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;
@ -418,9 +409,6 @@ void InstructionSelector::VisitCheckedStore(Node* node) {
case MachineRepresentation::kTagged: // Fall through.
case MachineRepresentation::kWord64: // Fall through.
case MachineRepresentation::kSimd128: // Fall through.
case MachineRepresentation::kSimd1x4: // Fall through.
case MachineRepresentation::kSimd1x8: // Fall through.
case MachineRepresentation::kSimd1x16: // Fall through.
case MachineRepresentation::kNone:
UNREACHABLE();
return;

6
src/machine-type.cc
View File

@ -32,12 +32,6 @@ const char* MachineReprToString(MachineRepresentation rep) {
return "kRepFloat64";
case MachineRepresentation::kSimd128:
return "kRepSimd128";
case MachineRepresentation::kSimd1x4:
return "kRepSimd1x4";
case MachineRepresentation::kSimd1x8:
return "kRepSimd1x8";
case MachineRepresentation::kSimd1x16:
return "kRepSimd1x16";
case MachineRepresentation::kTaggedSigned:
return "kRepTaggedSigned";
case MachineRepresentation::kTaggedPointer:

31
src/machine-type.h
View File

@ -29,11 +29,8 @@ enum class MachineRepresentation {
kFloat32,
kFloat64,
kSimd128,
kSimd1x4, // SIMD boolean vector types.
kSimd1x8,
kSimd1x16,
kFirstFPRepresentation = kFloat32,
kLastRepresentation = kSimd1x16
kLastRepresentation = kSimd128
};
static_assert(static_cast<int>(MachineRepresentation::kLastRepresentation) <
@ -130,16 +127,6 @@ class MachineType {
static MachineType Simd128() {
return MachineType(MachineRepresentation::kSimd128, MachineSemantic::kNone);
}
static MachineType Simd1x4() {
return MachineType(MachineRepresentation::kSimd1x4, MachineSemantic::kNone);
}
static MachineType Simd1x8() {
return MachineType(MachineRepresentation::kSimd1x8, MachineSemantic::kNone);
}
static MachineType Simd1x16() {
return MachineType(MachineRepresentation::kSimd1x16,
MachineSemantic::kNone);
}
static MachineType Pointer() {
return MachineType(PointerRepresentation(), MachineSemantic::kNone);
}
@ -186,16 +173,6 @@ class MachineType {
static MachineType RepSimd128() {
return MachineType(MachineRepresentation::kSimd128, MachineSemantic::kNone);
}
static MachineType RepSimd1x4() {
return MachineType(MachineRepresentation::kSimd1x4, MachineSemantic::kNone);
}
static MachineType RepSimd1x8() {
return MachineType(MachineRepresentation::kSimd1x8, MachineSemantic::kNone);
}
static MachineType RepSimd1x16() {
return MachineType(MachineRepresentation::kSimd1x16,
MachineSemantic::kNone);
}
static MachineType RepTagged() {
return MachineType(MachineRepresentation::kTagged, MachineSemantic::kNone);
}
@ -224,12 +201,6 @@ class MachineType {
return MachineType::Float64();
case MachineRepresentation::kSimd128:
return MachineType::Simd128();
case MachineRepresentation::kSimd1x4:
return MachineType::Simd1x4();
case MachineRepresentation::kSimd1x8:
return MachineType::Simd1x8();
case MachineRepresentation::kSimd1x16:
return MachineType::Simd1x16();
case MachineRepresentation::kTagged:
return MachineType::AnyTagged();
case MachineRepresentation::kTaggedSigned:

9
src/wasm/function-body-decoder-impl.h
View File

@ -152,15 +152,6 @@ struct BlockTypeOperand {
case kLocalS128:
*result = kWasmS128;
return true;
case kLocalS1x4:
*result = kWasmS1x4;
return true;
case kLocalS1x8:
*result = kWasmS1x8;
return true;
case kLocalS1x16:
*result = kWasmS1x16;
return true;
default:
*result = kWasmStmt;
return false;

15
src/wasm/function-body-decoder.cc
View File

@ -228,15 +228,6 @@ class WasmDecoder : public Decoder {
case kLocalS128:
type = kWasmS128;
break;
case kLocalS1x4:
type = kWasmS1x4;
break;
case kLocalS1x8:
type = kWasmS1x8;
break;
case kLocalS1x16:
type = kWasmS1x16;
break;
default:
decoder->error(decoder->pc() - 1, "invalid local type");
return false;
@ -761,12 +752,6 @@ class WasmFullDecoder : public WasmDecoder {
return builder_->Float64Constant(0);
case kWasmS128:
return builder_->S128Zero();
case kWasmS1x4:
return builder_->S1x4Zero();
case kWasmS1x8:
return builder_->S1x8Zero();
case kWasmS1x16:
return builder_->S1x16Zero();
default:
UNREACHABLE();
}

6
src/wasm/module-decoder.cc
View File

@ -1168,12 +1168,6 @@ class ModuleDecoder : public Decoder {
switch (t) {
case kLocalS128:
return kWasmS128;
case kLocalS1x4:
return kWasmS1x4;
case kLocalS1x8:
return kWasmS1x8;
case kLocalS1x16:
return kWasmS1x16;
default:
break;
}

16
src/wasm/wasm-opcodes.cc
View File

@ -218,28 +218,14 @@ const char* WasmOpcodes::OpcodeName(WasmOpcode opcode) {
CASE_S128_OP(Or, "or")
CASE_S128_OP(Xor, "xor")
CASE_S128_OP(Not, "not")
CASE_S128_OP(Select, "select")
CASE_S32x4_OP(Shuffle, "shuffle")
CASE_S32x4_OP(Select, "select")
CASE_S16x8_OP(Shuffle, "shuffle")
CASE_S16x8_OP(Select, "select")
CASE_S8x16_OP(Shuffle, "shuffle")
CASE_S8x16_OP(Select, "select")
CASE_S1x4_OP(And, "and")
CASE_S1x4_OP(Or, "or")
CASE_S1x4_OP(Xor, "xor")
CASE_S1x4_OP(Not, "not")
CASE_S1x4_OP(AnyTrue, "any_true")
CASE_S1x4_OP(AllTrue, "all_true")
CASE_S1x8_OP(And, "and")
CASE_S1x8_OP(Or, "or")
CASE_S1x8_OP(Xor, "xor")
CASE_S1x8_OP(Not, "not")
CASE_S1x8_OP(AnyTrue, "any_true")
CASE_S1x8_OP(AllTrue, "all_true")
CASE_S1x16_OP(And, "and")
CASE_S1x16_OP(Or, "or")
CASE_S1x16_OP(Xor, "xor")
CASE_S1x16_OP(Not, "not")
CASE_S1x16_OP(AnyTrue, "any_true")
CASE_S1x16_OP(AllTrue, "all_true")

165
src/wasm/wasm-opcodes.h
View File

@ -21,10 +21,7 @@ enum ValueTypeCode {
kLocalI64 = 0x7e,
kLocalF32 = 0x7d,
kLocalF64 = 0x7c,
kLocalS128 = 0x7b,
kLocalS1x4 = 0x7a,
kLocalS1x8 = 0x79,
kLocalS1x16 = 0x78
kLocalS128 = 0x7b
};
// Type code for multi-value block types.
@ -39,9 +36,6 @@ constexpr ValueType kWasmI64 = MachineRepresentation::kWord64;
constexpr ValueType kWasmF32 = MachineRepresentation::kFloat32;
constexpr ValueType kWasmF64 = MachineRepresentation::kFloat64;
constexpr ValueType kWasmS128 = MachineRepresentation::kSimd128;
constexpr ValueType kWasmS1x4 = MachineRepresentation::kSimd1x4;
constexpr ValueType kWasmS1x8 = MachineRepresentation::kSimd1x8;
constexpr ValueType kWasmS1x16 = MachineRepresentation::kSimd1x16;
constexpr ValueType kWasmVar = MachineRepresentation::kTagged;
using FunctionSig = Signature<ValueType>;
@ -294,12 +288,12 @@ constexpr WasmCodePosition kNoCodePosition = -1;
V(F32x4Mul, 0xe50a, s_ss) \
V(F32x4Min, 0xe50c, s_ss) \
V(F32x4Max, 0xe50d, s_ss) \
V(F32x4Eq, 0xe510, s1x4_ss) \
V(F32x4Ne, 0xe511, s1x4_ss) \
V(F32x4Lt, 0xe512, s1x4_ss) \
V(F32x4Le, 0xe513, s1x4_ss) \
V(F32x4Gt, 0xe514, s1x4_ss) \
V(F32x4Ge, 0xe515, s1x4_ss) \
V(F32x4Eq, 0xe510, s_ss) \
V(F32x4Ne, 0xe511, s_ss) \
V(F32x4Lt, 0xe512, s_ss) \
V(F32x4Le, 0xe513, s_ss) \
V(F32x4Gt, 0xe514, s_ss) \
V(F32x4Ge, 0xe515, s_ss) \
V(F32x4SConvertI32x4, 0xe519, s_s) \
V(F32x4UConvertI32x4, 0xe51a, s_s) \
V(I32x4Splat, 0xe51b, s_i) \
@ -310,12 +304,12 @@ constexpr WasmCodePosition kNoCodePosition = -1;
V(I32x4Mul, 0xe521, s_ss) \
V(I32x4MinS, 0xe522, s_ss) \
V(I32x4MaxS, 0xe523, s_ss) \
V(I32x4Eq, 0xe526, s1x4_ss) \
V(I32x4Ne, 0xe527, s1x4_ss) \
V(I32x4LtS, 0xe528, s1x4_ss) \
V(I32x4LeS, 0xe529, s1x4_ss) \
V(I32x4GtS, 0xe52a, s1x4_ss) \
V(I32x4GeS, 0xe52b, s1x4_ss) \
V(I32x4Eq, 0xe526, s_ss) \
V(I32x4Ne, 0xe527, s_ss) \
V(I32x4LtS, 0xe528, s_ss) \
V(I32x4LeS, 0xe529, s_ss) \
V(I32x4GtS, 0xe52a, s_ss) \
V(I32x4GeS, 0xe52b, s_ss) \
V(I32x4SConvertF32x4, 0xe52f, s_s) \
V(I32x4UConvertF32x4, 0xe537, s_s) \
V(I32x4SConvertI16x8Low, 0xe594, s_s) \
@ -324,10 +318,10 @@ constexpr WasmCodePosition kNoCodePosition = -1;
V(I32x4UConvertI16x8High, 0xe597, s_s) \
V(I32x4MinU, 0xe530, s_ss) \
V(I32x4MaxU, 0xe531, s_ss) \
V(I32x4LtU, 0xe533, s1x4_ss) \
V(I32x4LeU, 0xe534, s1x4_ss) \
V(I32x4GtU, 0xe535, s1x4_ss) \
V(I32x4GeU, 0xe536, s1x4_ss) \
V(I32x4LtU, 0xe533, s_ss) \
V(I32x4LeU, 0xe534, s_ss) \
V(I32x4GtU, 0xe535, s_ss) \
V(I32x4GeU, 0xe536, s_ss) \
V(I16x8Splat, 0xe538, s_i) \
V(I16x8Neg, 0xe53b, s_s) \
V(I16x8Add, 0xe53c, s_ss) \
@ -338,20 +332,20 @@ constexpr WasmCodePosition kNoCodePosition = -1;
V(I16x8Mul, 0xe540, s_ss) \
V(I16x8MinS, 0xe541, s_ss) \
V(I16x8MaxS, 0xe542, s_ss) \
V(I16x8Eq, 0xe545, s1x8_ss) \
V(I16x8Ne, 0xe546, s1x8_ss) \
V(I16x8LtS, 0xe547, s1x8_ss) \
V(I16x8LeS, 0xe548, s1x8_ss) \
V(I16x8GtS, 0xe549, s1x8_ss) \
V(I16x8GeS, 0xe54a, s1x8_ss) \
V(I16x8Eq, 0xe545, s_ss) \
V(I16x8Ne, 0xe546, s_ss) \
V(I16x8LtS, 0xe547, s_ss) \
V(I16x8LeS, 0xe548, s_ss) \
V(I16x8GtS, 0xe549, s_ss) \
V(I16x8GeS, 0xe54a, s_ss) \
V(I16x8AddSaturateU, 0xe54e, s_ss) \
V(I16x8SubSaturateU, 0xe54f, s_ss) \
V(I16x8MinU, 0xe550, s_ss) \
V(I16x8MaxU, 0xe551, s_ss) \
V(I16x8LtU, 0xe553, s1x8_ss) \
V(I16x8LeU, 0xe554, s1x8_ss) \
V(I16x8GtU, 0xe555, s1x8_ss) \
V(I16x8GeU, 0xe556, s1x8_ss) \
V(I16x8LtU, 0xe553, s_ss) \
V(I16x8LeU, 0xe554, s_ss) \
V(I16x8GtU, 0xe555, s_ss) \
V(I16x8GeU, 0xe556, s_ss) \
V(I16x8SConvertI32x4, 0xe598, s_ss) \
V(I16x8UConvertI32x4, 0xe599, s_ss) \
V(I16x8SConvertI8x16Low, 0xe59a, s_s) \
@ -367,47 +361,33 @@ constexpr WasmCodePosition kNoCodePosition = -1;
V(I8x16Mul, 0xe55f, s_ss) \
V(I8x16MinS, 0xe560, s_ss) \
V(I8x16MaxS, 0xe561, s_ss) \
V(I8x16Eq, 0xe564, s1x16_ss) \
V(I8x16Ne, 0xe565, s1x16_ss) \
V(I8x16LtS, 0xe566, s1x16_ss) \
V(I8x16LeS, 0xe567, s1x16_ss) \
V(I8x16GtS, 0xe568, s1x16_ss) \
V(I8x16GeS, 0xe569, s1x16_ss) \
V(I8x16Eq, 0xe564, s_ss) \
V(I8x16Ne, 0xe565, s_ss) \
V(I8x16LtS, 0xe566, s_ss) \
V(I8x16LeS, 0xe567, s_ss) \
V(I8x16GtS, 0xe568, s_ss) \
V(I8x16GeS, 0xe569, s_ss) \
V(I8x16AddSaturateU, 0xe56d, s_ss) \
V(I8x16SubSaturateU, 0xe56e, s_ss) \
V(I8x16MinU, 0xe56f, s_ss) \
V(I8x16MaxU, 0xe570, s_ss) \
V(I8x16LtU, 0xe572, s1x16_ss) \
V(I8x16LeU, 0xe573, s1x16_ss) \
V(I8x16GtU, 0xe574, s1x16_ss) \
V(I8x16GeU, 0xe575, s1x16_ss) \
V(I8x16LtU, 0xe572, s_ss) \
V(I8x16LeU, 0xe573, s_ss) \
V(I8x16GtU, 0xe574, s_ss) \
V(I8x16GeU, 0xe575, s_ss) \
V(I8x16SConvertI16x8, 0xe59e, s_ss) \
V(I8x16UConvertI16x8, 0xe59f, s_ss) \
V(S128And, 0xe576, s_ss) \
V(S128Or, 0xe577, s_ss) \
V(S128Xor, 0xe578, s_ss) \
V(S128Not, 0xe579, s_s) \
V(S32x4Select, 0xe52c, s_s1x4ss) \
V(S16x8Select, 0xe54b, s_s1x8ss) \
V(S8x16Select, 0xe56a, s_s1x16ss) \
V(S1x4And, 0xe580, s1x4_s1x4s1x4) \
V(S1x4Or, 0xe581, s1x4_s1x4s1x4) \
V(S1x4Xor, 0xe582, s1x4_s1x4s1x4) \
V(S1x4Not, 0xe583, s1x4_s1x4) \
V(S1x4AnyTrue, 0xe584, i_s1x4) \
V(S1x4AllTrue, 0xe585, i_s1x4) \
V(S1x8And, 0xe586, s1x8_s1x8s1x8) \
V(S1x8Or, 0xe587, s1x8_s1x8s1x8) \
V(S1x8Xor, 0xe588, s1x8_s1x8s1x8) \
V(S1x8Not, 0xe589, s1x8_s1x8) \
V(S1x8AnyTrue, 0xe58a, i_s1x8) \
V(S1x8AllTrue, 0xe58b, i_s1x8) \
V(S1x16And, 0xe58c, s1x16_s1x16s1x16) \
V(S1x16Or, 0xe58d, s1x16_s1x16s1x16) \
V(S1x16Xor, 0xe58e, s1x16_s1x16s1x16) \
V(S1x16Not, 0xe58f, s1x16_s1x16) \
V(S1x16AnyTrue, 0xe590, i_s1x16) \
V(S1x16AllTrue, 0xe591, i_s1x16)
V(S128Select, 0xe52c, s_sss) \
V(S1x4AnyTrue, 0xe584, i_s) \
V(S1x4AllTrue, 0xe585, i_s) \
V(S1x8AnyTrue, 0xe58a, i_s) \
V(S1x8AllTrue, 0xe58b, i_s) \
V(S1x16AnyTrue, 0xe590, i_s) \
V(S1x16AllTrue, 0xe591, i_s)
#define FOREACH_SIMD_1_OPERAND_OPCODE(V) \
V(F32x4ExtractLane, 0xe501, _) \
@ -515,28 +495,14 @@ constexpr WasmCodePosition kNoCodePosition = -1;
V(f_if, kWasmF32, kWasmI32, kWasmF32) \
V(l_il, kWasmI64, kWasmI32, kWasmI64)
#define FOREACH_SIMD_SIGNATURE(V) \
V(s_s, kWasmS128, kWasmS128) \
V(s_f, kWasmS128, kWasmF32) \
V(s_ss, kWasmS128, kWasmS128, kWasmS128) \
V(s1x4_ss, kWasmS1x4, kWasmS128, kWasmS128) \
V(s1x8_ss, kWasmS1x8, kWasmS128, kWasmS128) \
V(s1x16_ss, kWasmS1x16, kWasmS128, kWasmS128) \
V(s_i, kWasmS128, kWasmI32) \
V(s_si, kWasmS128, kWasmS128, kWasmI32) \
V(i_s, kWasmI32, kWasmS128) \
V(i_s1x4, kWasmI32, kWasmS1x4) \
V(i_s1x8, kWasmI32, kWasmS1x8) \
V(i_s1x16, kWasmI32, kWasmS1x16) \
V(s_s1x4ss, kWasmS128, kWasmS1x4, kWasmS128, kWasmS128) \
V(s_s1x8ss, kWasmS128, kWasmS1x8, kWasmS128, kWasmS128) \
V(s_s1x16ss, kWasmS128, kWasmS1x16, kWasmS128, kWasmS128) \
V(s1x4_s1x4, kWasmS1x4, kWasmS1x4) \
V(s1x4_s1x4s1x4, kWasmS1x4, kWasmS1x4, kWasmS1x4) \
V(s1x8_s1x8, kWasmS1x8, kWasmS1x8) \
V(s1x8_s1x8s1x8, kWasmS1x8, kWasmS1x8, kWasmS1x8) \
V(s1x16_s1x16, kWasmS1x16, kWasmS1x16) \
V(s1x16_s1x16s1x16, kWasmS1x16, kWasmS1x16, kWasmS1x16)
#define FOREACH_SIMD_SIGNATURE(V) \
V(s_s, kWasmS128, kWasmS128) \
V(s_f, kWasmS128, kWasmF32) \
V(s_ss, kWasmS128, kWasmS128, kWasmS128) \
V(s_i, kWasmS128, kWasmI32) \
V(s_si, kWasmS128, kWasmS128, kWasmI32) \
V(i_s, kWasmI32, kWasmS128) \
V(s_sss, kWasmS128, kWasmS128, kWasmS128, kWasmS128)
#define FOREACH_PREFIX(V) \
V(Simd, 0xe5) \
@ -604,12 +570,6 @@ class V8_EXPORT_PRIVATE WasmOpcodes {
return kLocalF64;
case kWasmS128:
return kLocalS128;
case kWasmS1x4:
return kLocalS1x4;
case kWasmS1x8:
return kLocalS1x8;
case kWasmS1x16:
return kLocalS1x16;
case kWasmStmt:
return kLocalVoid;
default:
@ -629,12 +589,6 @@ class V8_EXPORT_PRIVATE WasmOpcodes {
return MachineType::Float64();
case kWasmS128:
return MachineType::Simd128();
case kWasmS1x4:
return MachineType::Simd1x4();
case kWasmS1x8:
return MachineType::Simd1x8();
case kWasmS1x16:
return MachineType::Simd1x16();
case kWasmStmt:
return MachineType::None();
default:
@ -656,12 +610,6 @@ class V8_EXPORT_PRIVATE WasmOpcodes {
return kWasmF64;
case MachineRepresentation::kSimd128:
return kWasmS128;
case MachineRepresentation::kSimd1x4:
return kWasmS1x4;
case MachineRepresentation::kSimd1x8:
return kWasmS1x8;
case MachineRepresentation::kSimd1x16:
return kWasmS1x16;
default:
UNREACHABLE();
}
@ -678,9 +626,6 @@ class V8_EXPORT_PRIVATE WasmOpcodes {
case kWasmF64:
return 'd';
case kWasmS128:
case kWasmS1x4:
case kWasmS1x8:
case kWasmS1x16:
return 's';
case kWasmStmt:
return 'v';
@ -703,12 +648,6 @@ class V8_EXPORT_PRIVATE WasmOpcodes {
return "f64";
case kWasmS128:
return "s128";
case kWasmS1x4:
return "s1x4";
case kWasmS1x8:
return "s1x8";
case kWasmS1x16:
return "s1x16";
case kWasmStmt:
return "<stmt>";
case kWasmVar:

146
test/cctest/wasm/test-run-wasm-simd.cc
View File

@ -368,14 +368,12 @@ T RecipSqrt(T a) {
#define WASM_SIMD_SHIFT_OP(op, shift, x) x, WASM_SIMD_OP(op), TO_BYTE(shift)
#define WASM_SIMD_CONCAT_OP(op, bytes, x, y) \
x, y, WASM_SIMD_OP(op), TO_BYTE(bytes)
#define WASM_SIMD_SELECT(format, x, y, z) \
x, y, z, WASM_SIMD_OP(kExprS##format##Select)
#define WASM_SIMD_SELECT(format, x, y, z) x, y, z, WASM_SIMD_OP(kExprS128Select)
// Since boolean vectors can't be checked directly, materialize them into
// integer vectors using a Select operation.
#define WASM_SIMD_MATERIALIZE_BOOLS(format, x) \
x, WASM_SIMD_I##format##_SPLAT(WASM_ONE), \
WASM_SIMD_I##format##_SPLAT(WASM_ZERO), \
WASM_SIMD_OP(kExprS##format##Select)
WASM_SIMD_I##format##_SPLAT(WASM_ZERO), WASM_SIMD_OP(kExprS128Select)
#define WASM_SIMD_F32x4_SPLAT(x) x, WASM_SIMD_OP(kExprF32x4Splat)
#define WASM_SIMD_F32x4_EXTRACT_LANE(lane, x) \
@ -1495,8 +1493,9 @@ WASM_SIMD_TEST(I8x16ShrU) {
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_MIPS || \
V8_TARGET_ARCH_MIPS64
// Test Select by making a mask where the first two lanes are true and the rest
// false, and comparing for non-equality with zero to materialize a bool vector.
// Test Select by making a mask where the 0th and 3rd lanes are true and the
// rest false, and comparing for non-equality with zero to materialize a boolean
// vector.
#define WASM_SIMD_SELECT_TEST(format) \
WASM_SIMD_TEST(S##format##Select) { \
WasmRunner<int32_t, int32_t, int32_t> r(kExecuteCompiled); \
@ -1532,14 +1531,45 @@ WASM_SIMD_TEST(I8x16ShrU) {
}
WASM_SIMD_SELECT_TEST(32x4)
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_MIPS ||
// V8_TARGET_ARCH_MIPS64
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_MIPS || \
V8_TARGET_ARCH_MIPS64
WASM_SIMD_SELECT_TEST(16x8)
WASM_SIMD_SELECT_TEST(8x16)
// Test Select by making a mask where the 0th and 3rd lanes are non-zero and the
// rest 0. The mask is not the result of a comparison op.
#define WASM_SIMD_NON_CANONICAL_SELECT_TEST(format) \
WASM_SIMD_TEST(S##format##NonCanonicalSelect) { \
WasmRunner<int32_t, int32_t, int32_t, int32_t> r(kExecuteCompiled); \
byte val1 = 0; \
byte val2 = 1; \
byte combined = 2; \
byte src1 = r.AllocateLocal(kWasmS128); \
byte src2 = r.AllocateLocal(kWasmS128); \
byte zero = r.AllocateLocal(kWasmS128); \
byte mask = r.AllocateLocal(kWasmS128); \
BUILD(r, \
WASM_SET_LOCAL(src1, \
WASM_SIMD_I##format##_SPLAT(WASM_GET_LOCAL(val1))), \
WASM_SET_LOCAL(src2, \
WASM_SIMD_I##format##_SPLAT(WASM_GET_LOCAL(val2))), \
WASM_SET_LOCAL(zero, WASM_SIMD_I##format##_SPLAT(WASM_ZERO)), \
WASM_SET_LOCAL(mask, WASM_SIMD_I##format##_REPLACE_LANE( \
1, WASM_GET_LOCAL(zero), WASM_I32V(0xF))), \
WASM_SET_LOCAL(mask, WASM_SIMD_I##format##_REPLACE_LANE( \
2, WASM_GET_LOCAL(mask), WASM_I32V(0xF))), \
WASM_SET_LOCAL(mask, WASM_SIMD_SELECT(format, WASM_GET_LOCAL(mask), \
WASM_GET_LOCAL(src1), \
WASM_GET_LOCAL(src2))), \
WASM_SIMD_CHECK_LANE(I##format, mask, I32, val2, 0), \
WASM_SIMD_CHECK_LANE(I##format, mask, I32, combined, 1), \
WASM_SIMD_CHECK_LANE(I##format, mask, I32, combined, 2), \
WASM_SIMD_CHECK_LANE(I##format, mask, I32, val2, 3), WASM_ONE); \
\
CHECK_EQ(1, r.Call(0x12, 0x34, 0x32)); \
}
WASM_SIMD_NON_CANONICAL_SELECT_TEST(32x4)
WASM_SIMD_NON_CANONICAL_SELECT_TEST(16x8)
WASM_SIMD_NON_CANONICAL_SELECT_TEST(8x16)
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_MIPS ||
// V8_TARGET_ARCH_MIPS64
@ -1880,98 +1910,6 @@ WASM_SIMD_BOOL_REDUCTION_TEST(32x4, 4)
WASM_SIMD_BOOL_REDUCTION_TEST(16x8, 8)
WASM_SIMD_BOOL_REDUCTION_TEST(8x16, 16)
#define WASM_SIMD_UNOP_HELPER(format, lanes, lane_size) \
void RunS1x##lanes##UnOpTest(WasmOpcode simd_op, \
Int##lane_size##UnOp expected_op) { \
WasmRunner<int32_t, int32_t, int32_t> r(kExecuteCompiled); \
byte a = 0; \
byte expected = 1; \
byte zero = r.AllocateLocal(kWasmS128); \
byte simd = r.AllocateLocal(kWasmS128); \
BUILD( \
r, WASM_SET_LOCAL(zero, WASM_SIMD_I##format##_SPLAT(WASM_ZERO)), \
WASM_SET_LOCAL(simd, WASM_SIMD_I##format##_SPLAT(WASM_GET_LOCAL(a))), \
WASM_SET_LOCAL( \
simd, \
WASM_SIMD_MATERIALIZE_BOOLS( \
format, WASM_SIMD_UNOP( \
simd_op, WASM_SIMD_BINOP(kExprI##format##Ne, \
WASM_GET_LOCAL(simd), \
WASM_GET_LOCAL(zero))))), \
WASM_SIMD_CHECK_SPLAT##lanes(I##format, simd, I32, expected), \
WASM_ONE); \
\
for (int i = 0; i <= 1; i++) { \
CHECK_EQ(1, r.Call(i, expected_op(i))); \
} \
}
WASM_SIMD_UNOP_HELPER(32x4, 4, 32);
WASM_SIMD_UNOP_HELPER(16x8, 8, 16);
WASM_SIMD_UNOP_HELPER(8x16, 16, 8);
#undef WASM_SIMD_UNOP_HELPER
WASM_SIMD_TEST(S1x4Not) { RunS1x4UnOpTest(kExprS1x4Not, LogicalNot); }
WASM_SIMD_TEST(S1x8Not) { RunS1x8UnOpTest(kExprS1x8Not, LogicalNot); }
WASM_SIMD_TEST(S1x16Not) { RunS1x16UnOpTest(kExprS1x16Not, LogicalNot); }
#define WASM_SIMD_BINOP_HELPER(format, lanes, lane_size) \
void RunS1x##lanes##BinOpTest(WasmOpcode simd_op, \
Int##lane_size##BinOp expected_op) { \
WasmRunner<int32_t, int32_t, int32_t, int32_t> r(kExecuteCompiled); \
byte a = 0; \
byte b = 1; \
byte expected = 2; \
byte zero = r.AllocateLocal(kWasmS128); \
byte simd0 = r.AllocateLocal(kWasmS128); \
byte simd1 = r.AllocateLocal(kWasmS128); \
BUILD( \
r, WASM_SET_LOCAL(zero, WASM_SIMD_I##format##_SPLAT(WASM_ZERO)), \
WASM_SET_LOCAL(simd0, WASM_SIMD_I##format##_SPLAT(WASM_GET_LOCAL(a))), \
WASM_SET_LOCAL(simd1, WASM_SIMD_I##format##_SPLAT(WASM_GET_LOCAL(b))), \
WASM_SET_LOCAL( \
simd1, \
WASM_SIMD_MATERIALIZE_BOOLS( \
format, \
WASM_SIMD_BINOP( \
simd_op, \
WASM_SIMD_BINOP(kExprI##format##Ne, WASM_GET_LOCAL(simd0), \
WASM_GET_LOCAL(zero)), \
WASM_SIMD_BINOP(kExprI##format##Ne, WASM_GET_LOCAL(simd1), \
WASM_GET_LOCAL(zero))))), \
WASM_SIMD_CHECK_SPLAT##lanes(I##format, simd1, I32, expected), \
WASM_ONE); \
\
for (int i = 0; i <= 1; i++) { \
for (int j = 0; j <= 1; j++) { \
CHECK_EQ(1, r.Call(i, j, expected_op(i, j))); \
} \
} \
}
WASM_SIMD_BINOP_HELPER(32x4, 4, 32);
WASM_SIMD_BINOP_HELPER(16x8, 8, 16);
WASM_SIMD_BINOP_HELPER(8x16, 16, 8);
#undef WASM_SIMD_BINOP_HELPER
WASM_SIMD_TEST(S1x4And) { RunS1x4BinOpTest(kExprS1x4And, And); }
WASM_SIMD_TEST(S1x4Or) { RunS1x4BinOpTest(kExprS1x4Or, Or); }
WASM_SIMD_TEST(S1x4Xor) { RunS1x4BinOpTest(kExprS1x4Xor, Xor); }
WASM_SIMD_TEST(S1x8And) { RunS1x8BinOpTest(kExprS1x8And, And); }
WASM_SIMD_TEST(S1x8Or) { RunS1x8BinOpTest(kExprS1x8Or, Or); }
WASM_SIMD_TEST(S1x8Xor) { RunS1x8BinOpTest(kExprS1x8Xor, Xor); }
WASM_SIMD_TEST(S1x16And) { RunS1x16BinOpTest(kExprS1x16And, And); }
WASM_SIMD_TEST(S1x16Or) { RunS1x16BinOpTest(kExprS1x16Or, Or); }
WASM_SIMD_TEST(S1x16Xor) { RunS1x16BinOpTest(kExprS1x16Xor, Xor); }
#endif // !V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
#if V8_TARGET_ARCH_ARM || SIMD_LOWERING_TARGET || V8_TARGET_ARCH_MIPS || \