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[ARM] Assembler should assemble vzip/vuzp.32 as vtrn.

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LOG=N
BUG=v8:6020

Review-Url: https://codereview.chromium.org/2808233002
Cr-Commit-Position: refs/heads/master@{#44690}
This commit is contained in:
bbudge 2017-04-18 07:30:19 -07:00 committed by Commit bot
parent 42b2eb0e0e
commit 39f8e0c74a
1 changed files with 16 additions and 8 deletions
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24
src/arm/assembler-arm.cc
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@ -4642,10 +4642,14 @@ static Instr EncodeNeonSizedOp(NeonSizedOp op, NeonRegType reg_type,
}
void Assembler::vzip(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) {
DCHECK(IsEnabled(NEON));
// vzip.<size>(Dn, Dm) SIMD zip (interleave).
// Instruction details available in ARM DDI 0406C.b, A8-1102.
emit(EncodeNeonSizedOp(VZIP, NEON_D, size, src1.code(), src2.code()));
if (size == Neon32) { // vzip.32 Dd, Dm is a pseudo-op for vtrn.32 Dd, Dm.
vtrn(size, src1, src2);
} else {
DCHECK(IsEnabled(NEON));
// vzip.<size>(Dn, Dm) SIMD zip (interleave).
// Instruction details available in ARM DDI 0406C.b, A8-1102.
emit(EncodeNeonSizedOp(VZIP, NEON_D, size, src1.code(), src2.code()));
}
}
void Assembler::vzip(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) {
@ -4656,10 +4660,14 @@ void Assembler::vzip(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) {
}
void Assembler::vuzp(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) {
DCHECK(IsEnabled(NEON));
// vuzp.<size>(Dn, Dm) SIMD un-zip (de-interleave).
// Instruction details available in ARM DDI 0406C.b, A8-1100.
emit(EncodeNeonSizedOp(VUZP, NEON_D, size, src1.code(), src2.code()));
if (size == Neon32) { // vuzp.32 Dd, Dm is a pseudo-op for vtrn.32 Dd, Dm.
vtrn(size, src1, src2);
} else {
DCHECK(IsEnabled(NEON));
// vuzp.<size>(Dn, Dm) SIMD un-zip (de-interleave).
// Instruction details available in ARM DDI 0406C.b, A8-1100.
emit(EncodeNeonSizedOp(VUZP, NEON_D, size, src1.code(), src2.code()));
}
}
void Assembler::vuzp(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) {