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s390: [wasm-simd] Implement vbperm simulation

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Change-Id: Ied5f36130aae65631ccb05c3bbef4ca9ab88fbc8
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2219275
Reviewed-by: Junliang Yan <jyan@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#68073}
This commit is contained in:
Milad Farazmand 2020-05-29 13:04:51 +00:00 committed by Commit Bot
parent 0a25442140
commit 3e72573ca8
2 changed files with 53 additions and 7 deletions
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25
src/compiler/backend/s390/code-generator-s390.cc
View File

@ -4186,8 +4186,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kS390_I32x4BitMask: {
#ifdef V8_TARGET_BIG_ENDIAN
__ lgfi(kScratchReg, Operand(0x204060));
__ aih(kScratchReg, Operand(0x80808080)); // Zeroing the high bits
__ iihf(kScratchReg, Operand(0x80808080)); // Zeroing the high bits.
#else
__ lgfi(kScratchReg, Operand(0x80808080));
__ iihf(kScratchReg, Operand(0x60402000));
#endif
__ vlvg(kScratchDoubleReg, kScratchReg, MemOperand(r0, 1), Condition(3));
__ vbperm(kScratchDoubleReg, i.InputSimd128Register(0), kScratchDoubleReg,
Condition(0), Condition(0), Condition(0));
@ -4196,8 +4201,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kS390_I16x8BitMask: {
#ifdef V8_TARGET_BIG_ENDIAN
__ lgfi(kScratchReg, Operand(0x40506070));
__ aih(kScratchReg, Operand(0x102030));
__ iihf(kScratchReg, Operand(0x102030));
#else
__ lgfi(kScratchReg, Operand(0x30201000));
__ iihf(kScratchReg, Operand(0x70605040));
#endif
__ vlvg(kScratchDoubleReg, kScratchReg, MemOperand(r0, 1), Condition(3));
__ vbperm(kScratchDoubleReg, i.InputSimd128Register(0), kScratchDoubleReg,
Condition(0), Condition(0), Condition(0));
@ -4206,10 +4216,17 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kS390_I8x16BitMask: {
#ifdef V8_TARGET_BIG_ENDIAN
__ lgfi(r0, Operand(0x60687078));
__ aih(r0, Operand(0x40485058));
__ iihf(r0, Operand(0x40485058));
__ lgfi(ip, Operand(0x20283038));
__ aih(ip, Operand(0x81018));
__ iihf(ip, Operand(0x81018));
#else
__ lgfi(ip, Operand(0x58504840));
__ iihf(ip, Operand(0x78706860));
__ lgfi(r0, Operand(0x18100800));
__ iihf(r0, Operand(0x38302820));
#endif
__ vlvgp(kScratchDoubleReg, ip, r0);
__ vbperm(kScratchDoubleReg, i.InputSimd128Register(0), kScratchDoubleReg,
Condition(0), Condition(0), Condition(0));

35
src/execution/s390/simulator-s390.cc
View File

@ -785,9 +785,10 @@ void Simulator::EvalTableInit() {
V(vlc, VLC, 0xE7DE) /* type = VRR_A VECTOR LOAD COMPLEMENT */ \
V(vsel, VSEL, 0xE78D) /* type = VRR_E VECTOR SELECT */ \
V(vperm, VPERM, 0xE78C) /* type = VRR_E VECTOR PERMUTE */ \
V(vtm, VTM, 0xE7D8) /* type = VRR_A VECTOR TEST UNDER MASK */ \
V(vesl, VESL, 0xE730) /* type = VRS_A VECTOR ELEMENT SHIFT LEFT */ \
V(veslv, VESLV, 0xE770) /* type = VRR_C VECTOR ELEMENT SHIFT LEFT */ \
V(vbperm, VBPERM, 0xE785) /* type = VRR_C VECTOR BIT PERMUTE */ \
V(vtm, VTM, 0xE7D8) /* type = VRR_A VECTOR TEST UNDER MASK */ \
V(vesl, VESL, 0xE730) /* type = VRS_A VECTOR ELEMENT SHIFT LEFT */ \
V(veslv, VESLV, 0xE770) /* type = VRR_C VECTOR ELEMENT SHIFT LEFT */ \
V(vesrl, VESRL, \
0xE738) /* type = VRS_A VECTOR ELEMENT SHIFT RIGHT LOGICAL */ \
V(vesrlv, VESRLV, \
@ -3702,6 +3703,34 @@ EVALUATE(VPERM) {
return length;
}
EVALUATE(VBPERM) {
DCHECK_OPCODE(VBPERM);
DECODE_VRR_C_INSTRUCTION(r1, r2, r3, m6, m5, m4);
USE(m4);
USE(m5);
USE(m6);
uint16_t result_bits = 0;
for (int i = 0; i < kSimd128Size; i++) {
result_bits <<= 1;
uint8_t selected_bit_index = get_simd_register_by_lane<uint8_t>(r3, i);
unsigned __int128 src_bits =
*(reinterpret_cast<__int128*>(get_simd_register(r2).int8));
if (selected_bit_index < (kSimd128Size * kBitsPerByte)) {
unsigned __int128 bit_value =
(src_bits << selected_bit_index) >> (kSimd128Size * kBitsPerByte - 1);
result_bits |= bit_value;
}
}
set_simd_register_by_lane<uint64_t>(r1, 0, 0);
set_simd_register_by_lane<uint64_t>(r1, 1, 0);
// Write back in bytes to avoid endianness problems.
set_simd_register_by_lane<uint8_t>(r1, 6,
static_cast<uint8_t>(result_bits >> 8));
set_simd_register_by_lane<uint8_t>(
r1, 7, static_cast<uint8_t>((result_bits << 8) >> 8));
return length;
}
EVALUATE(VSEL) {
DCHECK_OPCODE(VSEL);
DECODE_VRR_E_INSTRUCTION(r1, r2, r3, r4, m6, m5);