s390: [wasm-simd] Implement F64x2 simd operations
Also adding to and modifying some of the F32x4 operations. Change-Id: Ia57dcd70a3bad2f1ec4ccc64ff2cb02b9c83aa22 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2081832 Reviewed-by: Junliang Yan <jyan@ca.ibm.com> Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com> Cr-Commit-Position: refs/heads/master@{#66539}
This commit is contained in:
Milad Farazmand
Commit Bot
parent
ae340e19fe
commit
40406eb649
@ -2900,6 +2900,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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ASSEMBLE_ATOMIC64_COMP_EXCHANGE_WORD64();
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break;
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// vector replicate element
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case kS390_F64x2Splat: {
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__ vrep(i.OutputSimd128Register(), i.InputDoubleRegister(0), Operand(0),
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Condition(3));
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break;
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}
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case kS390_F32x4Splat: {
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#ifdef V8_TARGET_BIG_ENDIAN
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__ vrep(i.OutputSimd128Register(), i.InputDoubleRegister(0), Operand(0),
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@ -2929,6 +2934,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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break;
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}
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// vector extract element
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case kS390_F64x2ExtractLane: {
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__ vrep(i.OutputDoubleRegister(), i.InputSimd128Register(0),
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Operand(1 - i.InputInt8(1)), Condition(3));
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break;
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}
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case kS390_F32x4ExtractLane: {
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__ vrep(i.OutputDoubleRegister(), i.InputSimd128Register(0),
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Operand(3 - i.InputInt8(1)), Condition(2));
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@ -2945,8 +2955,9 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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break;
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}
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case kS390_I16x8ExtractLaneS: {
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__ vlgv(i.OutputRegister(), i.InputSimd128Register(0),
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__ vlgv(kScratchReg, i.InputSimd128Register(0),
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MemOperand(r0, 7 - i.InputInt8(1)), Condition(1));
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__ lghr(i.OutputRegister(), kScratchReg);
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break;
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}
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case kS390_I8x16ExtractLaneU: {
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@ -2955,21 +2966,32 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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break;
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}
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case kS390_I8x16ExtractLaneS: {
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__ vlgv(i.OutputRegister(), i.InputSimd128Register(0),
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__ vlgv(kScratchReg, i.InputSimd128Register(0),
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MemOperand(r0, 15 - i.InputInt8(1)), Condition(0));
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__ lgbr(i.OutputRegister(), kScratchReg);
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break;
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}
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// vector replace element
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case kS390_F64x2ReplaceLane: {
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Simd128Register src = i.InputSimd128Register(0);
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Simd128Register dst = i.OutputSimd128Register();
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__ vlr(kScratchDoubleReg, src, Condition(0), Condition(0), Condition(0));
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__ vlgv(kScratchReg, i.InputDoubleRegister(2), MemOperand(r0, 0),
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Condition(3));
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__ vlvg(kScratchDoubleReg, kScratchReg,
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MemOperand(r0, 1 - i.InputInt8(1)), Condition(3));
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__ vlr(dst, kScratchDoubleReg, Condition(0), Condition(0), Condition(0));
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break;
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}
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case kS390_F32x4ReplaceLane: {
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Simd128Register src = i.InputSimd128Register(0);
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Simd128Register dst = i.OutputSimd128Register();
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if (src != dst) {
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__ vlr(dst, src, Condition(0), Condition(0), Condition(0));
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}
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__ lgdr(kScratchReg, i.InputDoubleRegister(2));
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__ srlg(kScratchReg, kScratchReg, Operand(32));
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__ vlvg(i.OutputSimd128Register(), kScratchReg,
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__ vlr(kScratchDoubleReg, src, Condition(0), Condition(0), Condition(0));
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__ vlgv(kScratchReg, i.InputDoubleRegister(2), MemOperand(r0, 0),
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Condition(2));
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__ vlvg(kScratchDoubleReg, kScratchReg,
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MemOperand(r0, 3 - i.InputInt8(1)), Condition(2));
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__ vlr(dst, kScratchDoubleReg, Condition(0), Condition(0), Condition(0));
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break;
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}
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case kS390_I32x4ReplaceLane: {
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@ -3003,6 +3025,42 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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break;
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}
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// vector binops
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case kS390_F64x2Add: {
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__ vfa(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1), Condition(0), Condition(0),
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Condition(3));
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break;
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}
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case kS390_F64x2Sub: {
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__ vfs(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1), Condition(0), Condition(0),
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Condition(3));
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break;
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}
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case kS390_F64x2Mul: {
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__ vfm(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1), Condition(0), Condition(0),
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Condition(3));
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break;
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}
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case kS390_F64x2Div: {
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__ vfd(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1), Condition(0), Condition(0),
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Condition(3));
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break;
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}
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case kS390_F64x2Min: {
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__ vfmin(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1), Condition(1), Condition(0),
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Condition(3));
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break;
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}
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case kS390_F64x2Max: {
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__ vfmax(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1), Condition(1), Condition(0),
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Condition(3));
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break;
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}
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case kS390_F32x4Add: {
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__ vfa(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1), Condition(0), Condition(0),
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@ -3040,6 +3098,24 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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Condition(2));
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break;
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}
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case kS390_F32x4Div: {
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__ vfd(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1), Condition(0), Condition(0),
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Condition(2));
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break;
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}
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case kS390_F32x4Min: {
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__ vfmin(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1), Condition(1), Condition(0),
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Condition(2));
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break;
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}
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case kS390_F32x4Max: {
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__ vfmax(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1), Condition(1), Condition(0),
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Condition(2));
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break;
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}
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case kS390_I32x4Add: {
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__ va(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1), Condition(0), Condition(0),
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@ -3123,6 +3199,32 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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break;
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}
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// vector comparisons
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case kS390_F64x2Eq: {
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__ vfce(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1), Condition(0), Condition(0),
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Condition(3));
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break;
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}
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case kS390_F64x2Ne: {
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__ vfce(kScratchDoubleReg, i.InputSimd128Register(0),
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i.InputSimd128Register(1), Condition(0), Condition(0),
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Condition(3));
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__ vno(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg,
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Condition(0), Condition(0), Condition(3));
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break;
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}
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case kS390_F64x2Le: {
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__ vfche(i.OutputSimd128Register(), i.InputSimd128Register(1),
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i.InputSimd128Register(0), Condition(0), Condition(0),
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Condition(3));
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break;
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}
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case kS390_F64x2Lt: {
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__ vfch(i.OutputSimd128Register(), i.InputSimd128Register(1),
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i.InputSimd128Register(0), Condition(0), Condition(0),
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Condition(3));
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break;
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}
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case kS390_I32x4MinS: {
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__ vmn(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1), Condition(0), Condition(0),
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@ -3217,12 +3319,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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break;
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}
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case kS390_F32x4Ne: {
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__ vfce(i.OutputSimd128Register(), i.InputSimd128Register(0),
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__ vfce(kScratchDoubleReg, i.InputSimd128Register(0),
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i.InputSimd128Register(1), Condition(0), Condition(0),
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Condition(2));
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__ vno(i.OutputSimd128Register(), i.OutputSimd128Register(),
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i.OutputSimd128Register(), Condition(0), Condition(0),
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Condition(2));
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__ vno(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg,
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Condition(0), Condition(0), Condition(2));
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break;
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}
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case kS390_I32x4Ne: {
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@ -3392,6 +3493,21 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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break;
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}
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// vector unary ops
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case kS390_F64x2Abs: {
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__ vfpso(i.OutputSimd128Register(), i.InputSimd128Register(0),
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Condition(2), Condition(0), Condition(3));
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break;
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}
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case kS390_F64x2Neg: {
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__ vfpso(i.OutputSimd128Register(), i.InputSimd128Register(0),
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Condition(0), Condition(0), Condition(3));
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break;
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}
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case kS390_F64x2Sqrt: {
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__ vfsq(i.OutputSimd128Register(), i.InputSimd128Register(0),
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Condition(0), Condition(0), Condition(3));
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break;
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}
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case kS390_F32x4Abs: {
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__ vfpso(i.OutputSimd128Register(), i.InputSimd128Register(0),
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Condition(2), Condition(0), Condition(2));
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@ -3437,6 +3553,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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Condition(0), Condition(0), Condition(2));
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break;
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}
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case kS390_F32x4Sqrt: {
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__ vfsq(i.OutputSimd128Register(), i.InputSimd128Register(0),
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Condition(0), Condition(0), Condition(2));
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break;
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}
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case kS390_S128Not: {
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Simd128Register src = i.InputSimd128Register(0);
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Simd128Register dst = i.OutputSimd128Register();
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@ -197,6 +197,22 @@ namespace compiler {
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V(S390_Word64AtomicXorUint16) \
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V(S390_Word64AtomicXorUint32) \
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V(S390_Word64AtomicXorUint64) \
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V(S390_F64x2Splat) \
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V(S390_F64x2ReplaceLane) \
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V(S390_F64x2Abs) \
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V(S390_F64x2Neg) \
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V(S390_F64x2Sqrt) \
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V(S390_F64x2Add) \
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V(S390_F64x2Sub) \
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V(S390_F64x2Mul) \
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V(S390_F64x2Div) \
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V(S390_F64x2Eq) \
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V(S390_F64x2Ne) \
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V(S390_F64x2Lt) \
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V(S390_F64x2Le) \
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V(S390_F64x2Min) \
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V(S390_F64x2Max) \
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V(S390_F64x2ExtractLane) \
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V(S390_F32x4Splat) \
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V(S390_F32x4ExtractLane) \
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V(S390_F32x4ReplaceLane) \
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@ -214,6 +230,10 @@ namespace compiler {
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V(S390_F32x4RecipSqrtApprox) \
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V(S390_F32x4SConvertI32x4) \
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V(S390_F32x4UConvertI32x4) \
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V(S390_F32x4Sqrt) \
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V(S390_F32x4Div) \
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V(S390_F32x4Min) \
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V(S390_F32x4Max) \
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V(S390_I32x4Splat) \
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V(S390_I32x4ExtractLane) \
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V(S390_I32x4ReplaceLane) \
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@ -143,6 +143,22 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kS390_CompressSigned:
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case kS390_CompressPointer:
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case kS390_CompressAny:
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case kS390_F64x2Splat:
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case kS390_F64x2ReplaceLane:
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case kS390_F64x2Abs:
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case kS390_F64x2Neg:
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case kS390_F64x2Sqrt:
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case kS390_F64x2Add:
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case kS390_F64x2Sub:
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case kS390_F64x2Mul:
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case kS390_F64x2Div:
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case kS390_F64x2Eq:
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case kS390_F64x2Ne:
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case kS390_F64x2Lt:
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case kS390_F64x2Le:
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case kS390_F64x2Min:
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case kS390_F64x2Max:
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case kS390_F64x2ExtractLane:
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case kS390_F32x4Splat:
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case kS390_F32x4ExtractLane:
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case kS390_F32x4ReplaceLane:
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@ -160,6 +176,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kS390_F32x4RecipSqrtApprox:
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case kS390_F32x4SConvertI32x4:
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case kS390_F32x4UConvertI32x4:
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case kS390_F32x4Sqrt:
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case kS390_F32x4Div:
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case kS390_F32x4Min:
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case kS390_F32x4Max:
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case kS390_I32x4Splat:
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case kS390_I32x4ExtractLane:
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case kS390_I32x4ReplaceLane:
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@ -2519,12 +2519,23 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
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}
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#define SIMD_TYPES(V) \
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V(F64x2) \
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V(F32x4) \
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V(I32x4) \
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V(I16x8) \
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V(I8x16)
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#define SIMD_BINOP_LIST(V) \
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V(F64x2Add) \
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V(F64x2Sub) \
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V(F64x2Mul) \
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V(F64x2Div) \
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V(F64x2Eq) \
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V(F64x2Ne) \
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V(F64x2Lt) \
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V(F64x2Le) \
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V(F64x2Min) \
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V(F64x2Max) \
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V(F32x4Add) \
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V(F32x4AddHoriz) \
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V(F32x4Sub) \
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@ -2533,6 +2544,9 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
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V(F32x4Ne) \
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V(F32x4Lt) \
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V(F32x4Le) \
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V(F32x4Div) \
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V(F32x4Min) \
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V(F32x4Max) \
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V(I32x4Add) \
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V(I32x4AddHoriz) \
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V(I32x4Sub) \
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@ -2591,10 +2605,14 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
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V(S128Xor)
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#define SIMD_UNOP_LIST(V) \
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V(F64x2Abs) \
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V(F64x2Neg) \
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V(F64x2Sqrt) \
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V(F32x4Abs) \
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V(F32x4Neg) \
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V(F32x4RecipApprox) \
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V(F32x4RecipSqrtApprox) \
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V(F32x4Sqrt) \
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V(I32x4Neg) \
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V(I32x4SConvertI16x8Low) \
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V(I32x4SConvertI16x8High) \
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@ -2649,6 +2667,7 @@ SIMD_TYPES(SIMD_VISIT_SPLAT)
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Emit(kS390_##Type##ExtractLane##Sign, g.DefineAsRegister(node), \
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g.UseRegister(node->InputAt(0)), g.UseImmediate(lane)); \
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}
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SIMD_VISIT_EXTRACT_LANE(F64x2, )
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SIMD_VISIT_EXTRACT_LANE(F32x4, )
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SIMD_VISIT_EXTRACT_LANE(I32x4, )
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SIMD_VISIT_EXTRACT_LANE(I16x8, U)
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@ -2798,42 +2817,8 @@ void InstructionSelector::EmitPrepareResults(
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}
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}
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void InstructionSelector::VisitF32x4Sqrt(Node* node) { UNIMPLEMENTED(); }
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void InstructionSelector::VisitF32x4Div(Node* node) { UNIMPLEMENTED(); }
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void InstructionSelector::VisitF32x4Min(Node* node) { UNIMPLEMENTED(); }
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void InstructionSelector::VisitF32x4Max(Node* node) { UNIMPLEMENTED(); }
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void InstructionSelector::VisitS8x16Swizzle(Node* node) { UNIMPLEMENTED(); }
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void InstructionSelector::VisitF64x2Splat(Node* node) { UNIMPLEMENTED(); }
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void InstructionSelector::VisitF64x2ReplaceLane(Node* node) { UNIMPLEMENTED(); }
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void InstructionSelector::VisitF64x2Abs(Node* node) { UNIMPLEMENTED(); }
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void InstructionSelector::VisitF64x2Neg(Node* node) { UNIMPLEMENTED(); }
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void InstructionSelector::VisitF64x2Sqrt(Node* node) { UNIMPLEMENTED(); }
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void InstructionSelector::VisitF64x2Add(Node* node) { UNIMPLEMENTED(); }
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void InstructionSelector::VisitF64x2Sub(Node* node) { UNIMPLEMENTED(); }
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void InstructionSelector::VisitF64x2Mul(Node* node) { UNIMPLEMENTED(); }
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void InstructionSelector::VisitF64x2Div(Node* node) { UNIMPLEMENTED(); }
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void InstructionSelector::VisitF64x2Eq(Node* node) { UNIMPLEMENTED(); }
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|
||||
void InstructionSelector::VisitF64x2Ne(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitF64x2Lt(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitF64x2Le(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI64x2Neg(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI64x2Add(Node* node) { UNIMPLEMENTED(); }
|
||||
@ -2848,12 +2833,6 @@ void InstructionSelector::VisitI64x2ShrU(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI64x2Mul(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitF64x2Min(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitF64x2Max(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitF64x2ExtractLane(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitLoadTransform(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
// static
|
||||
|
||||
Loading…
Reference in New Issue
Block a user