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[riscv32] fix wasm-spec-test/i64.js

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Change-Id: Ib6982c7f9509cfcb24fcdcd4726caab5a642faa0
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3824663
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/main@{#82388}
This commit is contained in:
Lu Yahan 2022-08-11 15:12:44 +08:00 committed by V8 LUCI CQ
parent aa101ca18f
commit 41cc719643
3 changed files with 58 additions and 16 deletions
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70
src/codegen/riscv/macro-assembler-riscv.cc
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@ -2265,10 +2265,25 @@ void TurboAssembler::ShlPair(Register dst_low, Register dst_high,
void TurboAssembler::ShlPair(Register dst_low, Register dst_high,
Register src_low, Register src_high, int32_t shift,
Register scratch1, Register scratch2) {
UseScratchRegisterScope temps(this);
Register scratch3 = temps.Acquire();
li(scratch3, shift);
ShlPair(dst_low, dst_high, src_low, src_high, scratch3, scratch1, scratch2);
DCHECK_GE(63, shift);
DCHECK_NE(dst_low, src_low);
DCHECK_NE(dst_high, src_low);
if (shift == 0) {
Move(dst_high, src_high);
Move(dst_low, src_low);
} else if (shift == 32) {
Move(dst_high, src_low);
li(dst_low, Operand(0));
} else if (shift > 32) {
shift &= 0x1F;
slli(dst_high, src_low, shift);
li(dst_low, Operand(0));
} else {
slli(dst_high, src_high, shift);
slli(dst_low, src_low, shift);
srli(scratch1, src_low, 32 - shift);
Or(dst_high, dst_high, scratch1);
}
}
void TurboAssembler::ShrPair(Register dst_low, Register dst_high,
@ -2319,10 +2334,26 @@ void TurboAssembler::ShrPair(Register dst_low, Register dst_high,
void TurboAssembler::ShrPair(Register dst_low, Register dst_high,
Register src_low, Register src_high, int32_t shift,
Register scratch1, Register scratch2) {
UseScratchRegisterScope temps(this);
Register scratch3 = temps.Acquire();
li(scratch3, shift);
ShrPair(dst_low, dst_high, src_low, src_high, scratch3, scratch1, scratch2);
DCHECK_GE(63, shift);
DCHECK_NE(dst_low, src_high);
DCHECK_NE(dst_high, src_high);
if (shift == 32) {
mv(dst_low, src_high);
li(dst_high, Operand(0));
} else if (shift > 32) {
shift &= 0x1F;
srli(dst_low, src_high, shift);
li(dst_high, Operand(0));
} else if (shift == 0) {
Move(dst_low, src_low);
Move(dst_high, src_high);
} else {
srli(dst_low, src_low, shift);
srli(dst_high, src_high, shift);
slli(scratch1, src_high, 32 - shift);
Or(dst_low, dst_low, scratch1);
}
}
void TurboAssembler::SarPair(Register dst_low, Register dst_high,
@ -2371,10 +2402,25 @@ void TurboAssembler::SarPair(Register dst_low, Register dst_high,
void TurboAssembler::SarPair(Register dst_low, Register dst_high,
Register src_low, Register src_high, int32_t shift,
Register scratch1, Register scratch2) {
UseScratchRegisterScope temps(this);
Register scratch3 = temps.Acquire();
li(scratch3, shift);
SarPair(dst_low, dst_high, src_low, src_high, scratch3, scratch1, scratch2);
DCHECK_GE(63, shift);
DCHECK_NE(dst_low, src_high);
DCHECK_NE(dst_high, src_high);
shift = shift & 0x3F;
if (shift == 0) {
mv(dst_low, src_low);
mv(dst_high, src_high);
} else if (shift < 32) {
srli(dst_low, src_low, shift);
srai(dst_high, src_high, shift);
slli(scratch1, src_high, 32 - shift);
Or(dst_low, dst_low, scratch1);
} else if (shift == 32) {
srai(dst_high, src_high, 31);
mv(dst_low, src_high);
} else {
srai(dst_high, src_high, 31);
srai(dst_low, src_high, shift - 32);
}
}
#endif

1
src/compiler/backend/riscv/instruction-selector-riscv32.cc
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@ -1309,7 +1309,6 @@ InstructionSelector::SupportedMachineOperatorFlags() {
return flags | MachineOperatorBuilder::kWord32Ctz |
MachineOperatorBuilder::kWord32Ctz |
MachineOperatorBuilder::kWord32Popcnt |
MachineOperatorBuilder::kWord32ShiftIsSafe |
MachineOperatorBuilder::kInt32DivIsSafe |
MachineOperatorBuilder::kUint32DivIsSafe |
MachineOperatorBuilder::kFloat32RoundDown |

3
test/wasm-spec-tests/wasm-spec-tests.status
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@ -114,9 +114,6 @@
'simd*': [SKIP],
'func': ['variant == stress', SKIP],
'i64': ['variant == stress', SKIP],
'proposals/js-types/i64': ['variant == stress', SKIP],
'proposals/memory64/i64': ['variant == stress', SKIP],
}], # 'arch == riscv32'
['arch == ppc or arch == ppc64', {