AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

[MIPS] Remove function QuietNaN.

Browse Source 
After 54a1889, Bug:7464, the permission of the page is read only, but this function need write permission.

Since this function is not used, just remove it.

Change-Id: I5a5976ab773bd808920893bbd2e3d9796e89e804
Reviewed-on: https://chromium-review.googlesource.com/c/1490813
Reviewed-by: Predrag Rudic <prudic@wavecomp.com>
Commit-Queue: Yu Yin <xwafish@gmail.com>
Cr-Commit-Position: refs/heads/master@{#59995}
This commit is contained in:
Yu Yin 2019-02-27 17:44:32 +08:00 committed by Commit Bot
parent f93aef833c
commit 420bc3e37e
4 changed files with 0 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mips/assembler-mips.cc
View File

@ -4051,14 +4051,6 @@ Address Assembler::target_address_at(Address pc) {
}
// MIPS and ia32 use opposite encoding for qNaN and sNaN, such that ia32
// qNaN is a MIPS sNaN, and ia32 sNaN is MIPS qNaN. If running from a heap
// snapshot generated on ia32, the resulting MIPS sNaN must be quieted.
// OS::nan_value() returns a qNaN.
void Assembler::QuietNaN(HeapObject object) {
HeapNumber::cast(object)->set_value(std::numeric_limits<double>::quiet_NaN());
}
// On Mips, a target address is stored in a lui/ori instruction pair, each
// of which load 16 bits of the 32-bit address to a register.
// Patching the address must replace both instr, and flush the i-cache.

2
src/mips/assembler-mips.h
View File

@ -266,8 +266,6 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
// of that call in the instruction stream.
inline static Address target_address_from_return_address(Address pc);
static void QuietNaN(HeapObject nan);
// This sets the branch destination (which gets loaded at the call address).
// This is for calls and branches within generated code. The serializer
// has already deserialized the lui/ori instructions etc.

8
src/mips64/assembler-mips64.cc
View File

@ -4301,14 +4301,6 @@ Address Assembler::target_address_at(Address pc) {
}
// MIPS and ia32 use opposite encoding for qNaN and sNaN, such that ia32
// qNaN is a MIPS sNaN, and ia32 sNaN is MIPS qNaN. If running from a heap
// snapshot generated on ia32, the resulting MIPS sNaN must be quieted.
// OS::nan_value() returns a qNaN.
void Assembler::QuietNaN(HeapObject object) {
HeapNumber::cast(object)->set_value(std::numeric_limits<double>::quiet_NaN());
}
// On Mips64, a target address is stored in a 4-instruction sequence:
// 0: lui(rd, (j.imm64_ >> 32) & kImm16Mask);
// 1: ori(rd, rd, (j.imm64_ >> 16) & kImm16Mask);

2
src/mips64/assembler-mips64.h
View File

@ -267,8 +267,6 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
static void JumpLabelToJumpRegister(Address pc);
static void QuietNaN(HeapObject nan);
// This sets the branch destination (which gets loaded at the call address).
// This is for calls and branches within generated code. The serializer
// has already deserialized the lui/ori instructions etc.