PPC [liftoff]: Implement simd comparison ops
Change-Id: Id691009bddafdbb5a53c234fe00995b6e0733586 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3893417 Commit-Queue: Milad Farazmand <mfarazma@redhat.com> Reviewed-by: Junliang Yan <junyan@redhat.com> Cr-Commit-Position: refs/heads/main@{#83200}
This commit is contained in:
Milad Fa
V8 LUCI CQ
parent
35e58232e6
commit
429f959f3d
@ -3684,14 +3684,18 @@ void TurboAssembler::StoreF32LE(DoubleRegister dst, const MemOperand& mem,
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V(F64x2Sub, xvsubdp) \
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V(F64x2Mul, xvmuldp) \
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V(F64x2Div, xvdivdp) \
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V(F64x2Eq, xvcmpeqdp) \
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V(F32x4Add, vaddfp) \
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V(F32x4Sub, vsubfp) \
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V(F32x4Mul, xvmulsp) \
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V(F32x4Div, xvdivsp) \
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V(F32x4Min, vminfp) \
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V(F32x4Max, vmaxfp) \
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V(F32x4Eq, xvcmpeqsp) \
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V(I64x2Add, vaddudm) \
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V(I64x2Sub, vsubudm) \
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V(I64x2Eq, vcmpequd) \
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V(I64x2GtS, vcmpgtsd) \
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V(I32x4Add, vadduwm) \
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V(I32x4Sub, vsubuwm) \
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V(I32x4Mul, vmuluwm) \
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@ -3699,18 +3703,27 @@ void TurboAssembler::StoreF32LE(DoubleRegister dst, const MemOperand& mem,
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V(I32x4MinU, vminuw) \
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V(I32x4MaxS, vmaxsw) \
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V(I32x4MaxU, vmaxuw) \
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V(I32x4Eq, vcmpequw) \
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V(I32x4GtS, vcmpgtsw) \
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V(I32x4GtU, vcmpgtuw) \
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V(I16x8Add, vadduhm) \
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V(I16x8Sub, vsubuhm) \
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V(I16x8MinS, vminsh) \
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V(I16x8MinU, vminuh) \
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V(I16x8MaxS, vmaxsh) \
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V(I16x8MaxU, vmaxuh) \
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V(I16x8Eq, vcmpequh) \
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V(I16x8GtS, vcmpgtsh) \
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V(I16x8GtU, vcmpgtuh) \
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V(I8x16Add, vaddubm) \
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V(I8x16Sub, vsububm) \
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V(I8x16MinS, vminsb) \
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V(I8x16MinU, vminub) \
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V(I8x16MaxS, vmaxsb) \
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V(I8x16MaxU, vmaxub)
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V(I8x16MaxU, vmaxub) \
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V(I8x16Eq, vcmpequb) \
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V(I8x16GtS, vcmpgtsb) \
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V(I8x16GtU, vcmpgtub)
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#define EMIT_SIMD_BINOP(name, op) \
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void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
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@ -3996,6 +4009,107 @@ void TurboAssembler::F64x2Max(Simd128Register dst, Simd128Register src1,
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}
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#undef F64X2_MIN_MAX_NAN
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void TurboAssembler::F64x2Lt(Simd128Register dst, Simd128Register src1,
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Simd128Register src2) {
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xvcmpgtdp(dst, src2, src1);
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}
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void TurboAssembler::F64x2Le(Simd128Register dst, Simd128Register src1,
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Simd128Register src2) {
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xvcmpgedp(dst, src2, src1);
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}
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void TurboAssembler::F64x2Ne(Simd128Register dst, Simd128Register src1,
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Simd128Register src2, Simd128Register scratch) {
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xvcmpeqdp(scratch, src1, src2);
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vnor(dst, scratch, scratch);
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}
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void TurboAssembler::F32x4Lt(Simd128Register dst, Simd128Register src1,
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Simd128Register src2) {
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xvcmpgtsp(dst, src2, src1);
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}
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void TurboAssembler::F32x4Le(Simd128Register dst, Simd128Register src1,
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Simd128Register src2) {
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xvcmpgesp(dst, src2, src1);
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}
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void TurboAssembler::F32x4Ne(Simd128Register dst, Simd128Register src1,
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Simd128Register src2, Simd128Register scratch) {
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xvcmpeqsp(scratch, src1, src2);
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vnor(dst, scratch, scratch);
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}
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void TurboAssembler::I64x2Ne(Simd128Register dst, Simd128Register src1,
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Simd128Register src2, Simd128Register scratch) {
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vcmpequd(scratch, src1, src2);
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vnor(dst, scratch, scratch);
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}
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void TurboAssembler::I64x2GeS(Simd128Register dst, Simd128Register src1,
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Simd128Register src2, Simd128Register scratch) {
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vcmpgtsd(scratch, src2, src1);
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vnor(dst, scratch, scratch);
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}
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void TurboAssembler::I32x4Ne(Simd128Register dst, Simd128Register src1,
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Simd128Register src2, Simd128Register scratch) {
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vcmpequw(scratch, src1, src2);
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vnor(dst, scratch, scratch);
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}
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void TurboAssembler::I32x4GeS(Simd128Register dst, Simd128Register src1,
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Simd128Register src2, Simd128Register scratch) {
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vcmpgtsw(scratch, src2, src1);
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vnor(dst, scratch, scratch);
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}
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void TurboAssembler::I32x4GeU(Simd128Register dst, Simd128Register src1,
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Simd128Register src2, Simd128Register scratch) {
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vcmpequw(scratch, src1, src2);
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vcmpgtuw(dst, src1, src2);
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vor(dst, dst, scratch);
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}
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void TurboAssembler::I16x8Ne(Simd128Register dst, Simd128Register src1,
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Simd128Register src2, Simd128Register scratch) {
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vcmpequh(scratch, src1, src2);
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vnor(dst, scratch, scratch);
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}
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void TurboAssembler::I16x8GeS(Simd128Register dst, Simd128Register src1,
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Simd128Register src2, Simd128Register scratch) {
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vcmpgtsh(scratch, src2, src1);
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vnor(dst, scratch, scratch);
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}
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void TurboAssembler::I16x8GeU(Simd128Register dst, Simd128Register src1,
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Simd128Register src2, Simd128Register scratch) {
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vcmpequh(scratch, src1, src2);
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vcmpgtuh(dst, src1, src2);
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vor(dst, dst, scratch);
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}
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void TurboAssembler::I8x16Ne(Simd128Register dst, Simd128Register src1,
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Simd128Register src2, Simd128Register scratch) {
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vcmpequb(scratch, src1, src2);
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vnor(dst, scratch, scratch);
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}
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void TurboAssembler::I8x16GeS(Simd128Register dst, Simd128Register src1,
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Simd128Register src2, Simd128Register scratch) {
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vcmpgtsb(scratch, src2, src1);
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vnor(dst, scratch, scratch);
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}
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void TurboAssembler::I8x16GeU(Simd128Register dst, Simd128Register src1,
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Simd128Register src2, Simd128Register scratch) {
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vcmpequb(scratch, src1, src2);
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vcmpgtub(dst, src1, src2);
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vor(dst, dst, scratch);
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}
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Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3,
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Register reg4, Register reg5,
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Register reg6) {
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@ -1085,14 +1085,22 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
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V(F64x2Sub) \
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V(F64x2Mul) \
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V(F64x2Div) \
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V(F64x2Eq) \
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V(F64x2Lt) \
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V(F64x2Le) \
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V(F32x4Add) \
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V(F32x4Sub) \
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V(F32x4Mul) \
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V(F32x4Div) \
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V(F32x4Min) \
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V(F32x4Max) \
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V(F32x4Eq) \
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V(F32x4Lt) \
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V(F32x4Le) \
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V(I64x2Add) \
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V(I64x2Sub) \
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V(I64x2Eq) \
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V(I64x2GtS) \
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V(I32x4MinS) \
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V(I32x4MinU) \
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V(I32x4MaxS) \
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@ -1100,6 +1108,9 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
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V(I32x4Add) \
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V(I32x4Sub) \
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V(I32x4Mul) \
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V(I32x4Eq) \
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V(I32x4GtS) \
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V(I32x4GtU) \
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V(I16x8Add) \
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V(I16x8Sub) \
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V(I16x8Mul) \
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@ -1107,12 +1118,18 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
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V(I16x8MinU) \
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V(I16x8MaxS) \
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V(I16x8MaxU) \
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V(I16x8Eq) \
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V(I16x8GtS) \
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V(I16x8GtU) \
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V(I8x16Add) \
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V(I8x16Sub) \
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V(I8x16MinS) \
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V(I8x16MinU) \
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V(I8x16MaxS) \
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V(I8x16MaxU)
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V(I8x16MaxU) \
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V(I8x16Eq) \
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V(I8x16GtS) \
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V(I8x16GtU)
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#define PROTOTYPE_SIMD_BINOP(name) \
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void name(Simd128Register dst, Simd128Register src1, Simd128Register src2);
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@ -1179,6 +1196,32 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
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Simd128Register scratch1, Simd128Register scratch2);
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void F64x2Max(Simd128Register dst, Simd128Register src1, Simd128Register src2,
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Simd128Register scratch1, Simd128Register scratch2);
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void F64x2Ne(Simd128Register dst, Simd128Register src1, Simd128Register src2,
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Simd128Register scratch);
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void F32x4Ne(Simd128Register dst, Simd128Register src1, Simd128Register src2,
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Simd128Register scratch);
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void I64x2Ne(Simd128Register dst, Simd128Register src1, Simd128Register src2,
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Simd128Register scratch);
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void I64x2GeS(Simd128Register dst, Simd128Register src1, Simd128Register src2,
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Simd128Register scratch);
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void I32x4Ne(Simd128Register dst, Simd128Register src1, Simd128Register src2,
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Simd128Register scratch);
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void I32x4GeS(Simd128Register dst, Simd128Register src1, Simd128Register src2,
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Simd128Register scratch);
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void I32x4GeU(Simd128Register dst, Simd128Register src1, Simd128Register src2,
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Simd128Register scratch);
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void I16x8Ne(Simd128Register dst, Simd128Register src1, Simd128Register src2,
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Simd128Register scratch);
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void I16x8GeS(Simd128Register dst, Simd128Register src1, Simd128Register src2,
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Simd128Register scratch);
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void I16x8GeU(Simd128Register dst, Simd128Register src1, Simd128Register src2,
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Simd128Register scratch);
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void I8x16Ne(Simd128Register dst, Simd128Register src1, Simd128Register src2,
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Simd128Register scratch);
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void I8x16GeS(Simd128Register dst, Simd128Register src1, Simd128Register src2,
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Simd128Register scratch);
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void I8x16GeU(Simd128Register dst, Simd128Register src1, Simd128Register src2,
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Simd128Register scratch);
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private:
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static const int kSmiShift = kSmiTagSize + kSmiShiftSize;
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@ -2199,14 +2199,22 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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V(F64x2Sub) \
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V(F64x2Mul) \
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V(F64x2Div) \
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V(F64x2Eq) \
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V(F64x2Lt) \
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V(F64x2Le) \
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V(F32x4Add) \
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V(F32x4Sub) \
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V(F32x4Mul) \
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V(F32x4Div) \
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V(F32x4Min) \
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V(F32x4Max) \
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V(F32x4Eq) \
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V(F32x4Lt) \
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V(F32x4Le) \
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V(I64x2Add) \
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V(I64x2Sub) \
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V(I64x2Eq) \
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V(I64x2GtS) \
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V(I32x4Add) \
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V(I32x4Sub) \
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V(I32x4Mul) \
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@ -2214,6 +2222,9 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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V(I32x4MinU) \
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V(I32x4MaxS) \
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V(I32x4MaxU) \
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V(I32x4Eq) \
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V(I32x4GtS) \
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V(I32x4GtU) \
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V(I16x8Add) \
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V(I16x8Sub) \
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V(I16x8Mul) \
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@ -2221,12 +2232,18 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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V(I16x8MinU) \
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V(I16x8MaxS) \
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V(I16x8MaxU) \
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V(I16x8Eq) \
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V(I16x8GtS) \
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V(I16x8GtU) \
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V(I8x16Add) \
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V(I8x16Sub) \
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V(I8x16MinS) \
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V(I8x16MinU) \
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V(I8x16MaxS) \
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V(I8x16MaxU)
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V(I8x16MaxU) \
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V(I8x16Eq) \
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V(I8x16GtS) \
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V(I8x16GtU)
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#define EMIT_SIMD_BINOP(name) \
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case kPPC_##name: { \
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@ -2364,187 +2381,69 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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kScratchSimd128Reg2);
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break;
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}
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case kPPC_F64x2Eq: {
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__ xvcmpeqdp(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_F64x2Ne: {
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__ xvcmpeqdp(kScratchSimd128Reg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
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kScratchSimd128Reg);
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break;
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}
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case kPPC_F64x2Le: {
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__ xvcmpgedp(i.OutputSimd128Register(), i.InputSimd128Register(1),
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i.InputSimd128Register(0));
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break;
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}
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case kPPC_F64x2Lt: {
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__ xvcmpgtdp(i.OutputSimd128Register(), i.InputSimd128Register(1),
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i.InputSimd128Register(0));
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break;
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}
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case kPPC_F32x4Eq: {
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__ xvcmpeqsp(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_I64x2Eq: {
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__ vcmpequd(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_I32x4Eq: {
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__ vcmpequw(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_I16x8Eq: {
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__ vcmpequh(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_I8x16Eq: {
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__ vcmpequb(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ F64x2Ne(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1), kScratchSimd128Reg);
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break;
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}
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case kPPC_F32x4Ne: {
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__ xvcmpeqsp(kScratchSimd128Reg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
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kScratchSimd128Reg);
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__ F32x4Ne(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1), kScratchSimd128Reg);
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break;
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}
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case kPPC_I64x2Ne: {
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__ vcmpequd(kScratchSimd128Reg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
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kScratchSimd128Reg);
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break;
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}
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case kPPC_I32x4Ne: {
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__ vcmpequw(kScratchSimd128Reg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
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kScratchSimd128Reg);
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break;
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}
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case kPPC_I16x8Ne: {
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__ vcmpequh(kScratchSimd128Reg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
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kScratchSimd128Reg);
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break;
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}
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case kPPC_I8x16Ne: {
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__ vcmpequb(kScratchSimd128Reg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
|
||||
kScratchSimd128Reg);
|
||||
break;
|
||||
}
|
||||
case kPPC_F32x4Lt: {
|
||||
__ xvcmpgtsp(i.OutputSimd128Register(), i.InputSimd128Register(1),
|
||||
i.InputSimd128Register(0));
|
||||
break;
|
||||
}
|
||||
case kPPC_F32x4Le: {
|
||||
__ xvcmpgesp(i.OutputSimd128Register(), i.InputSimd128Register(1),
|
||||
i.InputSimd128Register(0));
|
||||
break;
|
||||
}
|
||||
case kPPC_I64x2GtS: {
|
||||
__ vcmpgtsd(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1));
|
||||
break;
|
||||
}
|
||||
case kPPC_I32x4GtS: {
|
||||
__ vcmpgtsw(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1));
|
||||
__ I64x2Ne(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1), kScratchSimd128Reg);
|
||||
break;
|
||||
}
|
||||
case kPPC_I64x2GeS: {
|
||||
__ vcmpgtsd(kScratchSimd128Reg, i.InputSimd128Register(1),
|
||||
i.InputSimd128Register(0));
|
||||
__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
|
||||
kScratchSimd128Reg);
|
||||
__ I64x2GeS(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1), kScratchSimd128Reg);
|
||||
break;
|
||||
}
|
||||
case kPPC_I32x4Ne: {
|
||||
__ I32x4Ne(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1), kScratchSimd128Reg);
|
||||
break;
|
||||
}
|
||||
case kPPC_I32x4GeS: {
|
||||
__ vcmpgtsw(kScratchSimd128Reg, i.InputSimd128Register(1),
|
||||
i.InputSimd128Register(0));
|
||||
__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
|
||||
kScratchSimd128Reg);
|
||||
break;
|
||||
}
|
||||
case kPPC_I32x4GtU: {
|
||||
__ vcmpgtuw(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1));
|
||||
|
||||
__ I32x4GeS(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1), kScratchSimd128Reg);
|
||||
break;
|
||||
}
|
||||
case kPPC_I32x4GeU: {
|
||||
__ vcmpequw(kScratchSimd128Reg, i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1));
|
||||
__ vcmpgtuw(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1));
|
||||
__ vor(i.OutputSimd128Register(), i.OutputSimd128Register(),
|
||||
kScratchSimd128Reg);
|
||||
__ I32x4GeU(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1), kScratchSimd128Reg);
|
||||
break;
|
||||
}
|
||||
case kPPC_I16x8GtS: {
|
||||
__ vcmpgtsh(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1));
|
||||
case kPPC_I16x8Ne: {
|
||||
__ I16x8Ne(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1), kScratchSimd128Reg);
|
||||
break;
|
||||
}
|
||||
case kPPC_I16x8GeS: {
|
||||
__ vcmpgtsh(kScratchSimd128Reg, i.InputSimd128Register(1),
|
||||
i.InputSimd128Register(0));
|
||||
__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
|
||||
kScratchSimd128Reg);
|
||||
break;
|
||||
}
|
||||
case kPPC_I16x8GtU: {
|
||||
__ vcmpgtuh(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1));
|
||||
__ I16x8GeS(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1), kScratchSimd128Reg);
|
||||
break;
|
||||
}
|
||||
case kPPC_I16x8GeU: {
|
||||
__ vcmpequh(kScratchSimd128Reg, i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1));
|
||||
__ vcmpgtuh(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1));
|
||||
__ vor(i.OutputSimd128Register(), i.OutputSimd128Register(),
|
||||
kScratchSimd128Reg);
|
||||
__ I16x8GeU(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1), kScratchSimd128Reg);
|
||||
break;
|
||||
}
|
||||
case kPPC_I8x16GtS: {
|
||||
__ vcmpgtsb(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1));
|
||||
case kPPC_I8x16Ne: {
|
||||
__ I8x16Ne(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1), kScratchSimd128Reg);
|
||||
break;
|
||||
}
|
||||
case kPPC_I8x16GeS: {
|
||||
__ vcmpgtsb(kScratchSimd128Reg, i.InputSimd128Register(1),
|
||||
i.InputSimd128Register(0));
|
||||
__ vnor(i.OutputSimd128Register(), kScratchSimd128Reg,
|
||||
kScratchSimd128Reg);
|
||||
break;
|
||||
}
|
||||
case kPPC_I8x16GtU: {
|
||||
__ vcmpgtub(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1));
|
||||
__ I8x16GeS(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1), kScratchSimd128Reg);
|
||||
break;
|
||||
}
|
||||
case kPPC_I8x16GeU: {
|
||||
__ vcmpequb(kScratchSimd128Reg, i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1));
|
||||
__ vcmpgtub(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1));
|
||||
__ vor(i.OutputSimd128Register(), i.OutputSimd128Register(),
|
||||
kScratchSimd128Reg);
|
||||
__ I8x16GeU(i.OutputSimd128Register(), i.InputSimd128Register(0),
|
||||
i.InputSimd128Register(1), kScratchSimd128Reg);
|
||||
break;
|
||||
}
|
||||
#define VECTOR_SHIFT(op) \
|
||||
|
||||
@ -1774,14 +1774,22 @@ bool LiftoffAssembler::emit_select(LiftoffRegister dst, Register condition,
|
||||
V(f64x2_sub, F64x2Sub) \
|
||||
V(f64x2_mul, F64x2Mul) \
|
||||
V(f64x2_div, F64x2Div) \
|
||||
V(f64x2_eq, F64x2Eq) \
|
||||
V(f64x2_lt, F64x2Lt) \
|
||||
V(f64x2_le, F64x2Le) \
|
||||
V(f32x4_add, F32x4Add) \
|
||||
V(f32x4_sub, F32x4Sub) \
|
||||
V(f32x4_mul, F32x4Mul) \
|
||||
V(f32x4_div, F32x4Div) \
|
||||
V(f32x4_min, F32x4Min) \
|
||||
V(f32x4_max, F32x4Max) \
|
||||
V(f32x4_eq, F32x4Eq) \
|
||||
V(f32x4_lt, F32x4Lt) \
|
||||
V(f32x4_le, F32x4Le) \
|
||||
V(i64x2_add, I64x2Add) \
|
||||
V(i64x2_sub, I64x2Sub) \
|
||||
V(i64x2_eq, I64x2Eq) \
|
||||
V(i64x2_gt_s, I64x2GtS) \
|
||||
V(i32x4_add, I32x4Add) \
|
||||
V(i32x4_sub, I32x4Sub) \
|
||||
V(i32x4_mul, I32x4Mul) \
|
||||
@ -1789,6 +1797,9 @@ bool LiftoffAssembler::emit_select(LiftoffRegister dst, Register condition,
|
||||
V(i32x4_min_u, I32x4MinU) \
|
||||
V(i32x4_max_s, I32x4MaxS) \
|
||||
V(i32x4_max_u, I32x4MaxU) \
|
||||
V(i32x4_eq, I32x4Eq) \
|
||||
V(i32x4_gt_s, I32x4GtS) \
|
||||
V(i32x4_gt_u, I32x4GtU) \
|
||||
V(i16x8_add, I16x8Add) \
|
||||
V(i16x8_sub, I16x8Sub) \
|
||||
V(i16x8_mul, I16x8Mul) \
|
||||
@ -1796,12 +1807,18 @@ bool LiftoffAssembler::emit_select(LiftoffRegister dst, Register condition,
|
||||
V(i16x8_min_u, I16x8MinU) \
|
||||
V(i16x8_max_s, I16x8MaxS) \
|
||||
V(i16x8_max_u, I16x8MaxU) \
|
||||
V(i16x8_eq, I16x8Eq) \
|
||||
V(i16x8_gt_s, I16x8GtS) \
|
||||
V(i16x8_gt_u, I16x8GtU) \
|
||||
V(i8x16_add, I8x16Add) \
|
||||
V(i8x16_sub, I8x16Sub) \
|
||||
V(i8x16_min_s, I8x16MinS) \
|
||||
V(i8x16_min_u, I8x16MinU) \
|
||||
V(i8x16_max_s, I8x16MaxS) \
|
||||
V(i8x16_max_u, I8x16MaxU)
|
||||
V(i8x16_max_u, I8x16MaxU) \
|
||||
V(i8x16_eq, I8x16Eq) \
|
||||
V(i8x16_gt_s, I8x16GtS) \
|
||||
V(i8x16_gt_u, I8x16GtU)
|
||||
|
||||
#define EMIT_SIMD_BINOP(name, op) \
|
||||
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister lhs, \
|
||||
@ -1968,6 +1985,84 @@ void LiftoffAssembler::emit_f64x2_max(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
kScratchSimd128Reg, kScratchSimd128Reg2);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_f64x2_ne(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
F64x2Ne(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
|
||||
kScratchSimd128Reg);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_f32x4_ne(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
F32x4Ne(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
|
||||
kScratchSimd128Reg);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i64x2_ne(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
I64x2Ne(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
|
||||
kScratchSimd128Reg);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i64x2_ge_s(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
I64x2GeS(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
|
||||
kScratchSimd128Reg);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i32x4_ne(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
I32x4Ne(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
|
||||
kScratchSimd128Reg);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i32x4_ge_s(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
I32x4GeS(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
|
||||
kScratchSimd128Reg);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i32x4_ge_u(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
I32x4GeU(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
|
||||
kScratchSimd128Reg);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i16x8_ne(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
I16x8Ne(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
|
||||
kScratchSimd128Reg);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i16x8_ge_s(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
I16x8GeS(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
|
||||
kScratchSimd128Reg);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i16x8_ge_u(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
I16x8GeU(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
|
||||
kScratchSimd128Reg);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i8x16_ne(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
I8x16Ne(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
|
||||
kScratchSimd128Reg);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i8x16_ge_s(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
I8x16GeS(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
|
||||
kScratchSimd128Reg);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i8x16_ge_u(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
I8x16GeU(dst.fp().toSimd(), lhs.fp().toSimd(), rhs.fp().toSimd(),
|
||||
kScratchSimd128Reg);
|
||||
}
|
||||
|
||||
void LiftoffAssembler::LoadTransform(LiftoffRegister dst, Register src_addr,
|
||||
Register offset_reg, uintptr_t offset_imm,
|
||||
LoadType type,
|
||||
@ -2553,156 +2648,6 @@ void LiftoffAssembler::emit_i8x16_add_sat_s(LiftoffRegister dst,
|
||||
bailout(kUnsupportedArchitecture, "emit_i8x16addsaturate_s");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i8x16_eq(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_i8x16_eq");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i8x16_ne(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_i8x16_ne");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i8x16_gt_s(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_i8x16gt_s");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i8x16_gt_u(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_i8x16gt_u");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i8x16_ge_s(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_i8x16ge_s");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i8x16_ge_u(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_i8x16ge_u");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i16x8_eq(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_i16x8_eq");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i16x8_ne(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_i16x8_ne");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i16x8_gt_s(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_i16x8gt_s");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i16x8_gt_u(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_i16x8gt_u");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i16x8_ge_s(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_i16x8ge_s");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i16x8_ge_u(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_i16x8ge_u");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i32x4_eq(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_i32x4_eq");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i32x4_ne(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_i32x4_ne");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i32x4_gt_s(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_i32x4gt_s");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i32x4_gt_u(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_32x4gt_u");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i32x4_ge_s(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_i32x4ge_s");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i32x4_ge_u(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_i32x4ge_u");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i64x2_eq(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kSimd, "i64x2.eq");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i64x2_ne(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kSimd, "i64x2_ne");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i64x2_gt_s(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kSimd, "i64x2.gt_s");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_i64x2_ge_s(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kSimd, "i64x2.ge_s");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_f32x4_eq(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_f32x4_eq");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_f32x4_ne(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_f32x4_ne");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_f32x4_lt(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_f32x4_lt");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_f32x4_le(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_f32x4_le");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_f64x2_eq(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_f64x2_eq");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_f64x2_ne(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_f64x2_ne");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_f64x2_lt(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_f64x2_lt");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_f64x2_le(LiftoffRegister dst, LiftoffRegister lhs,
|
||||
LiftoffRegister rhs) {
|
||||
bailout(kUnsupportedArchitecture, "emit_f64x2_le");
|
||||
}
|
||||
|
||||
void LiftoffAssembler::emit_s128_const(LiftoffRegister dst,
|
||||
const uint8_t imms[16]) {
|
||||
bailout(kUnsupportedArchitecture, "emit_s128_const");
|
||||
|
||||
Loading…
Reference in New Issue
Block a user