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[Liftoff][mips] Implement f32 and f64 set_cond instructions

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Also, implement supporting function for translating Condition to
MIPS FPUCondition.

Bug: v8:6600
Change-Id: I5a3497a8445e2fc5a18abd56a83cd1451c2c48ec
Reviewed-on: https://chromium-review.googlesource.com/1010163
Commit-Queue: Sreten Kovacevic <sreten.kovacevic@mips.com>
Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
Cr-Commit-Position: refs/heads/master@{#52573}
This commit is contained in:
sreten.kovacevic 2018-04-12 14:09:55 +02:00 committed by Commit Bot
parent 2b7e063f2a
commit 44007be068
2 changed files with 160 additions and 4 deletions
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82
src/wasm/baseline/mips/liftoff-assembler-mips.h
View File

@ -859,16 +859,94 @@ void LiftoffAssembler::emit_i64_set_cond(Condition cond, Register dst,
TurboAssembler::Move(dst, tmp);
}
namespace liftoff {
inline FPUCondition ConditionToConditionCmpFPU(bool& predicate,
Condition condition) {
switch (condition) {
case kEqual:
predicate = true;
return EQ;
case kUnequal:
predicate = false;
return EQ;
case kUnsignedLessThan:
predicate = true;
return OLT;
case kUnsignedGreaterEqual:
predicate = false;
return OLT;
case kUnsignedLessEqual:
predicate = true;
return OLE;
case kUnsignedGreaterThan:
predicate = false;
return OLE;
default:
predicate = true;
break;
}
UNREACHABLE();
}
}; // namespace liftoff
void LiftoffAssembler::emit_f32_set_cond(Condition cond, Register dst,
DoubleRegister lhs,
DoubleRegister rhs) {
BAILOUT("emit_f32_set_cond");
Label not_nan, cont;
TurboAssembler::CompareIsNanF32(lhs, rhs);
TurboAssembler::BranchFalseF(&not_nan);
// If one of the operands is NaN, return 1 for f32.ne, else 0.
if (cond == ne) {
TurboAssembler::li(dst, 1);
} else {
TurboAssembler::Move(dst, zero_reg);
}
TurboAssembler::Branch(&cont);
bind(&not_nan);
TurboAssembler::li(dst, 1);
bool predicate;
FPUCondition fcond = liftoff::ConditionToConditionCmpFPU(predicate, cond);
TurboAssembler::CompareF32(fcond, lhs, rhs);
if (predicate) {
TurboAssembler::Movf(dst, zero_reg);
} else {
TurboAssembler::Movt(dst, zero_reg);
}
bind(&cont);
}
void LiftoffAssembler::emit_f64_set_cond(Condition cond, Register dst,
DoubleRegister lhs,
DoubleRegister rhs) {
BAILOUT("emit_f64_set_cond");
Label not_nan, cont;
TurboAssembler::CompareIsNanF64(lhs, rhs);
TurboAssembler::BranchFalseF(&not_nan);
// If one of the operands is NaN, return 1 for f64.ne, else 0.
if (cond == ne) {
TurboAssembler::li(dst, 1);
} else {
TurboAssembler::Move(dst, zero_reg);
}
TurboAssembler::Branch(&cont);
bind(&not_nan);
TurboAssembler::li(dst, 1);
bool predicate;
FPUCondition fcond = liftoff::ConditionToConditionCmpFPU(predicate, cond);
TurboAssembler::CompareF64(fcond, lhs, rhs);
if (predicate) {
TurboAssembler::Movf(dst, zero_reg);
} else {
TurboAssembler::Movt(dst, zero_reg);
}
bind(&cont);
}
void LiftoffAssembler::StackCheck(Label* ool_code) {

82
src/wasm/baseline/mips64/liftoff-assembler-mips64.h
View File

@ -697,16 +697,94 @@ void LiftoffAssembler::emit_i64_set_cond(Condition cond, Register dst,
TurboAssembler::Move(dst, tmp);
}
namespace liftoff {
inline FPUCondition ConditionToConditionCmpFPU(bool& predicate,
Condition condition) {
switch (condition) {
case kEqual:
predicate = true;
return EQ;
case kUnequal:
predicate = false;
return EQ;
case kUnsignedLessThan:
predicate = true;
return OLT;
case kUnsignedGreaterEqual:
predicate = false;
return OLT;
case kUnsignedLessEqual:
predicate = true;
return OLE;
case kUnsignedGreaterThan:
predicate = false;
return OLE;
default:
predicate = true;
break;
}
UNREACHABLE();
}
}; // namespace liftoff
void LiftoffAssembler::emit_f32_set_cond(Condition cond, Register dst,
DoubleRegister lhs,
DoubleRegister rhs) {
BAILOUT("emit_f32_set_cond");
Label not_nan, cont;
TurboAssembler::CompareIsNanF32(lhs, rhs);
TurboAssembler::BranchFalseF(&not_nan);
// If one of the operands is NaN, return 1 for f32.ne, else 0.
if (cond == ne) {
TurboAssembler::li(dst, 1);
} else {
TurboAssembler::Move(dst, zero_reg);
}
TurboAssembler::Branch(&cont);
bind(&not_nan);
TurboAssembler::li(dst, 1);
bool predicate;
FPUCondition fcond = liftoff::ConditionToConditionCmpFPU(predicate, cond);
TurboAssembler::CompareF32(fcond, lhs, rhs);
if (predicate) {
TurboAssembler::Movf(dst, zero_reg);
} else {
TurboAssembler::Movt(dst, zero_reg);
}
bind(&cont);
}
void LiftoffAssembler::emit_f64_set_cond(Condition cond, Register dst,
DoubleRegister lhs,
DoubleRegister rhs) {
BAILOUT("emit_f64_set_cond");
Label not_nan, cont;
TurboAssembler::CompareIsNanF64(lhs, rhs);
TurboAssembler::BranchFalseF(&not_nan);
// If one of the operands is NaN, return 1 for f64.ne, else 0.
if (cond == ne) {
TurboAssembler::li(dst, 1);
} else {
TurboAssembler::Move(dst, zero_reg);
}
TurboAssembler::Branch(&cont);
bind(&not_nan);
TurboAssembler::li(dst, 1);
bool predicate;
FPUCondition fcond = liftoff::ConditionToConditionCmpFPU(predicate, cond);
TurboAssembler::CompareF64(fcond, lhs, rhs);
if (predicate) {
TurboAssembler::Movf(dst, zero_reg);
} else {
TurboAssembler::Movt(dst, zero_reg);
}
bind(&cont);
}
void LiftoffAssembler::StackCheck(Label* ool_code) {