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Move SSE instructions into list macro

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Bug: v8:9810
Change-Id: Ie7c497d8aae40db71c3039e457d0535fd8d5b3f1
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1872015
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64440}
This commit is contained in:
Ng Zhi An 2019-10-21 15:04:20 -07:00 committed by Commit Bot
parent 4eddc6c524
commit 44d68718b1
4 changed files with 50 additions and 208 deletions
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182
src/codegen/x64/assembler-x64.cc
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@ -2699,138 +2699,6 @@ void Assembler::emit_farith(int b1, int b2, int i) {
emit(b2 + i);
}
// SSE operations.
void Assembler::andps(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x54);
emit_sse_operand(dst, src);
}
void Assembler::andps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x54);
emit_sse_operand(dst, src);
}
void Assembler::andnps(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x55);
emit_sse_operand(dst, src);
}
void Assembler::andnps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x55);
emit_sse_operand(dst, src);
}
void Assembler::orps(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x56);
emit_sse_operand(dst, src);
}
void Assembler::orps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x56);
emit_sse_operand(dst, src);
}
void Assembler::xorps(XMMRegister dst, XMMRegister src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x57);
emit_sse_operand(dst, src);
}
void Assembler::xorps(XMMRegister dst, Operand src) {
DCHECK(!IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x57);
emit_sse_operand(dst, src);
}
void Assembler::addps(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x58);
emit_sse_operand(dst, src);
}
void Assembler::addps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x58);
emit_sse_operand(dst, src);
}
void Assembler::subps(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x5C);
emit_sse_operand(dst, src);
}
void Assembler::subps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x5C);
emit_sse_operand(dst, src);
}
void Assembler::mulps(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x59);
emit_sse_operand(dst, src);
}
void Assembler::mulps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x59);
emit_sse_operand(dst, src);
}
void Assembler::divps(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x5E);
emit_sse_operand(dst, src);
}
void Assembler::divps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x5E);
emit_sse_operand(dst, src);
}
// SSE 2 operations.
void Assembler::movd(XMMRegister dst, Register src) {
@ -4551,38 +4419,6 @@ void Assembler::pause() {
emit(0x90);
}
void Assembler::minps(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x5D);
emit_sse_operand(dst, src);
}
void Assembler::minps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x5D);
emit_sse_operand(dst, src);
}
void Assembler::maxps(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x5F);
emit_sse_operand(dst, src);
}
void Assembler::maxps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x5F);
emit_sse_operand(dst, src);
}
void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
@ -4687,6 +4523,24 @@ void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::sse_instr(XMMRegister dst, XMMRegister src, byte escape,
byte opcode) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(escape);
emit(opcode);
emit_sse_operand(dst, src);
}
void Assembler::sse_instr(XMMRegister dst, Operand src, byte escape,
byte opcode) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(escape);
emit(opcode);
emit_sse_operand(dst, src);
}
void Assembler::sse2_instr(XMMRegister dst, XMMRegister src, byte prefix,
byte escape, byte opcode) {
EnsureSpace ensure_space(this);

36
src/codegen/x64/assembler-x64.h
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@ -871,24 +871,6 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
void cvtlsi2ss(XMMRegister dst, Operand src);
void cvtlsi2ss(XMMRegister dst, Register src);
void andps(XMMRegister dst, XMMRegister src);
void andps(XMMRegister dst, Operand src);
void andnps(XMMRegister dst, XMMRegister src);
void andnps(XMMRegister dst, Operand src);
void orps(XMMRegister dst, XMMRegister src);
void orps(XMMRegister dst, Operand src);
void xorps(XMMRegister dst, XMMRegister src);
void xorps(XMMRegister dst, Operand src);
void addps(XMMRegister dst, XMMRegister src);
void addps(XMMRegister dst, Operand src);
void subps(XMMRegister dst, XMMRegister src);
void subps(XMMRegister dst, Operand src);
void mulps(XMMRegister dst, XMMRegister src);
void mulps(XMMRegister dst, Operand src);
void divps(XMMRegister dst, XMMRegister src);
void divps(XMMRegister dst, Operand src);
void movmskps(Register dst, XMMRegister src);
void vinstr(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2,
@ -896,6 +878,20 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
void vinstr(byte op, XMMRegister dst, XMMRegister src1, Operand src2,
SIMDPrefix pp, LeadingOpcode m, VexW w);
// SSE instructions
void sse_instr(XMMRegister dst, XMMRegister src, byte escape, byte opcode);
void sse_instr(XMMRegister dst, Operand src, byte escape, byte opcode);
#define DECLARE_SSE_INSTRUCTION(instruction, escape, opcode) \
void instruction(XMMRegister dst, XMMRegister src) { \
sse_instr(dst, src, 0x##escape, 0x##opcode); \
} \
void instruction(XMMRegister dst, Operand src) { \
sse_instr(dst, src, 0x##escape, 0x##opcode); \
}
SSE_INSTRUCTION_LIST(DECLARE_SSE_INSTRUCTION)
#undef DECLARE_SSE_INSTRUCTION
// SSE2 instructions
void sse2_instr(XMMRegister dst, XMMRegister src, byte prefix, byte escape,
byte opcode);
@ -1130,10 +1126,6 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
#undef SSE_CMP_P
void minps(XMMRegister dst, XMMRegister src);
void minps(XMMRegister dst, Operand src);
void maxps(XMMRegister dst, XMMRegister src);
void maxps(XMMRegister dst, Operand src);
void rcpps(XMMRegister dst, XMMRegister src);
void rcpps(XMMRegister dst, Operand src);
void rsqrtps(XMMRegister dst, XMMRegister src);

12
src/codegen/x64/sse-instr.h
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@ -5,6 +5,18 @@
#ifndef V8_CODEGEN_X64_SSE_INSTR_H_
#define V8_CODEGEN_X64_SSE_INSTR_H_
#define SSE_INSTRUCTION_LIST(V) \
V(andps, 0F, 54) \
V(andnps, 0F, 55) \
V(orps, 0F, 56) \
V(xorps, 0F, 57) \
V(addps, 0F, 58) \
V(mulps, 0F, 59) \
V(subps, 0F, 5C) \
V(minps, 0F, 5D) \
V(divps, 0F, 5E) \
V(maxps, 0F, 5F)
#define SSE2_INSTRUCTION_LIST(V) \
V(sqrtpd, 66, 0F, 51) \
V(andnpd, 66, 0F, 55) \

28
test/cctest/test-disasm-x64.cc
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@ -394,16 +394,6 @@ TEST(DisasmX64) {
__ movdqu(Operand(rsp, 12), xmm0);
__ shufps(xmm0, xmm9, 0x0);
// logic operation
__ andps(xmm0, xmm1);
__ andps(xmm0, Operand(rbx, rcx, times_4, 10000));
__ andnps(xmm0, xmm1);
__ andnps(xmm0, Operand(rbx, rcx, times_4, 10000));
__ orps(xmm0, xmm1);
__ orps(xmm0, Operand(rbx, rcx, times_4, 10000));
__ xorps(xmm0, xmm1);
__ xorps(xmm0, Operand(rbx, rcx, times_4, 10000));
// Arithmetic operation
__ addss(xmm1, xmm0);
__ addss(xmm1, Operand(rbx, rcx, times_4, 10000));
@ -419,17 +409,15 @@ TEST(DisasmX64) {
__ minss(xmm1, Operand(rbx, rcx, times_4, 10000));
__ sqrtss(xmm1, xmm0);
__ sqrtss(xmm1, Operand(rbx, rcx, times_4, 10000));
__ addps(xmm1, xmm0);
__ addps(xmm1, Operand(rbx, rcx, times_4, 10000));
__ subps(xmm1, xmm0);
__ subps(xmm1, Operand(rbx, rcx, times_4, 10000));
__ mulps(xmm1, xmm0);
__ mulps(xmm1, Operand(rbx, rcx, times_4, 10000));
__ divps(xmm1, xmm0);
__ divps(xmm1, Operand(rbx, rcx, times_4, 10000));
__ ucomiss(xmm0, xmm1);
__ ucomiss(xmm0, Operand(rbx, rcx, times_4, 10000));
#define EMIT_SSE_INSTR(instruction, notUsed1, notUsed2) \
__ instruction(xmm1, xmm0); \
__ instruction(xmm1, Operand(rbx, rcx, times_4, 10000));
SSE_INSTRUCTION_LIST(EMIT_SSE_INSTR)
#undef EMIT_SSE_INSTR
}
// SSE2 instructions
@ -583,10 +571,6 @@ TEST(DisasmX64) {
__ cmpnlepd(xmm5, xmm1);
__ cmpnlepd(xmm5, Operand(rbx, rcx, times_4, 10000));
__ minps(xmm5, xmm1);
__ minps(xmm5, Operand(rdx, 4));
__ maxps(xmm5, xmm1);
__ maxps(xmm5, Operand(rdx, 4));
__ rcpps(xmm5, xmm1);
__ rcpps(xmm5, Operand(rdx, 4));
__ sqrtps(xmm5, xmm1);