AuroraMiddleware/v8
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[arm64] Fix i/d cache line size confusion typo

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BUG=chromium:593867
LOG=y

Review URL: https://codereview.chromium.org/1783343002

Cr-Commit-Position: refs/heads/master@{#34719}
This commit is contained in:
jkummerow 2016-03-11 04:46:37 -08:00 committed by Commit bot
parent dd0e6ca04c
commit 474e6a3d6d
1 changed files with 2 additions and 2 deletions
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4
src/base/cpu.cc
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@ -656,8 +656,8 @@ CPU::CPU()
}
CacheLineSizes sizes;
icache_line_size_ = sizes.dcache_line_size();
dcache_line_size_ = sizes.icache_line_size();
icache_line_size_ = sizes.icache_line_size();
dcache_line_size_ = sizes.dcache_line_size();
#elif V8_HOST_ARCH_PPC