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[ptr-compr][turbofan] Bitcasting between Word32 and CompressedSigned

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We were going for 64 bits to go back to 32 bits. For example,
TruncateInt64ToInt32(BitcastTaggedSignedToWord(ChangeCompressedToTagged(x)))
when that doesn't modify the value at all.

In order to keep the machine graph verifier happy two bitcast operations
were introduced.

As a drive-by nit cleanup, we were having two empty lines between some
functions implementations in machine-operator-reducer.cc.

Bug: v8:7703
Change-Id: Ifaa0d656010fe4f6f6f4581a2bb6633f060245b7
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1749383
Commit-Queue: Santiago Aboy Solanes <solanes@chromium.org>
Reviewed-by: Georg Neis <neis@chromium.org>
Cr-Commit-Position: refs/heads/master@{#63191}
This commit is contained in:
Santiago Aboy Solanes 2019-08-13 14:49:00 +01:00 committed by Commit Bot
parent 69b1f07229
commit 475019f299
8 changed files with 59 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/compiler/backend/instruction-selector.cc
View File

@ -1506,6 +1506,12 @@ void InstructionSelector::VisitNode(Node* node) {
case IrOpcode::kBitcastWordToTaggedSigned:
return MarkAsRepresentation(MachineRepresentation::kTaggedSigned, node),
EmitIdentity(node);
case IrOpcode::kBitcastWord32ToCompressedSigned:
return MarkAsRepresentation(MachineRepresentation::kCompressedSigned,
node),
EmitIdentity(node);
case IrOpcode::kBitcastCompressedSignedToWord32:
return MarkAsWord32(node), EmitIdentity(node);
case IrOpcode::kChangeFloat32ToFloat64:
return MarkAsFloat64(node), VisitChangeFloat32ToFloat64(node);
case IrOpcode::kChangeInt32ToFloat64:

14
src/compiler/machine-graph-verifier.cc
View File

@ -245,6 +245,13 @@ class MachineRepresentationInferrer {
representation_vector_[node->id()] =
MachineRepresentation::kTaggedSigned;
break;
case IrOpcode::kBitcastWord32ToCompressedSigned:
representation_vector_[node->id()] =
MachineRepresentation::kCompressedSigned;
break;
case IrOpcode::kBitcastCompressedSignedToWord32:
representation_vector_[node->id()] = MachineRepresentation::kWord32;
break;
case IrOpcode::kWord32Equal:
case IrOpcode::kInt32LessThan:
case IrOpcode::kInt32LessThanOrEqual:
@ -430,6 +437,13 @@ class MachineRepresentationChecker {
case IrOpcode::kTaggedPoisonOnSpeculation:
CheckValueInputIsTagged(node, 0);
break;
case IrOpcode::kBitcastWord32ToCompressedSigned:
CheckValueInputRepresentationIs(node, 0,
MachineRepresentation::kWord32);
break;
case IrOpcode::kBitcastCompressedSignedToWord32:
CheckValueInputIsCompressed(node, 0);
break;
case IrOpcode::kTruncateFloat64ToWord32:
case IrOpcode::kTruncateFloat64ToUint32:
case IrOpcode::kTruncateFloat64ToFloat32:

46
src/compiler/machine-operator-reducer.cc
View File

@ -34,17 +34,14 @@ Node* MachineOperatorReducer::Float32Constant(volatile float value) {
return graph()->NewNode(common()->Float32Constant(value));
}
Node* MachineOperatorReducer::Float64Constant(volatile double value) {
return mcgraph()->Float64Constant(value);
}
Node* MachineOperatorReducer::Int32Constant(int32_t value) {
return mcgraph()->Int32Constant(value);
}
Node* MachineOperatorReducer::Int64Constant(int64_t value) {
return graph()->NewNode(common()->Int64Constant(value));
}
@ -70,23 +67,27 @@ Node* MachineOperatorReducer::Word32And(Node* lhs, Node* rhs) {
return reduction.Changed() ? reduction.replacement() : node;
}
Node* MachineOperatorReducer::Word32Sar(Node* lhs, uint32_t rhs) {
if (rhs == 0) return lhs;
return graph()->NewNode(machine()->Word32Sar(), lhs, Uint32Constant(rhs));
}
Node* MachineOperatorReducer::Word32Shr(Node* lhs, uint32_t rhs) {
if (rhs == 0) return lhs;
return graph()->NewNode(machine()->Word32Shr(), lhs, Uint32Constant(rhs));
}
Node* MachineOperatorReducer::Word32Equal(Node* lhs, Node* rhs) {
return graph()->NewNode(machine()->Word32Equal(), lhs, rhs);
}
Node* MachineOperatorReducer::BitcastWord32ToCompressedSigned(Node* value) {
return graph()->NewNode(machine()->BitcastWord32ToCompressedSigned(), value);
}
Node* MachineOperatorReducer::BitcastCompressedSignedToWord32(Node* value) {
return graph()->NewNode(machine()->BitcastCompressedSignedToWord32(), value);
}
Node* MachineOperatorReducer::Int32Add(Node* lhs, Node* rhs) {
Node* const node = graph()->NewNode(machine()->Int32Add(), lhs, rhs);
@ -94,19 +95,16 @@ Node* MachineOperatorReducer::Int32Add(Node* lhs, Node* rhs) {
return reduction.Changed() ? reduction.replacement() : node;
}
Node* MachineOperatorReducer::Int32Sub(Node* lhs, Node* rhs) {
Node* const node = graph()->NewNode(machine()->Int32Sub(), lhs, rhs);
Reduction const reduction = ReduceInt32Sub(node);
return reduction.Changed() ? reduction.replacement() : node;
}
Node* MachineOperatorReducer::Int32Mul(Node* lhs, Node* rhs) {
return graph()->NewNode(machine()->Int32Mul(), lhs, rhs);
}
Node* MachineOperatorReducer::Int32Div(Node* dividend, int32_t divisor) {
DCHECK_NE(0, divisor);
DCHECK_NE(std::numeric_limits<int32_t>::min(), divisor);
@ -122,7 +120,6 @@ Node* MachineOperatorReducer::Int32Div(Node* dividend, int32_t divisor) {
return Int32Add(Word32Sar(quotient, mag.shift), Word32Shr(dividend, 31));
}
Node* MachineOperatorReducer::Uint32Div(Node* dividend, uint32_t divisor) {
DCHECK_LT(0u, divisor);
// If the divisor is even, we can avoid using the expensive fixup by shifting
@ -146,7 +143,6 @@ Node* MachineOperatorReducer::Uint32Div(Node* dividend, uint32_t divisor) {
return quotient;
}
// Perform constant folding and strength reduction on machine operators.
Reduction MachineOperatorReducer::Reduce(Node* node) {
switch (node->opcode()) {
@ -664,6 +660,17 @@ Reduction MachineOperatorReducer::Reduce(Node* node) {
if (m.HasValue()) return ReplaceInt64(static_cast<uint64_t>(m.Value()));
break;
}
case IrOpcode::kChangeTaggedToCompressed: {
Int64Matcher m(node->InputAt(0));
if (m.IsBitcastWordToTaggedSigned()) {
Int64Matcher n(m.node()->InputAt(0));
if (n.IsChangeInt32ToInt64()) {
DCHECK(machine()->Is64() && SmiValuesAre31Bits());
return Replace(BitcastWord32ToCompressedSigned(n.node()->InputAt(0)));
}
}
break;
}
case IrOpcode::kTruncateFloat64ToWord32: {
Float64Matcher m(node->InputAt(0));
if (m.HasValue()) return ReplaceInt32(DoubleToInt32(m.Value()));
@ -674,6 +681,13 @@ Reduction MachineOperatorReducer::Reduce(Node* node) {
Int64Matcher m(node->InputAt(0));
if (m.HasValue()) return ReplaceInt32(static_cast<int32_t>(m.Value()));
if (m.IsChangeInt32ToInt64()) return Replace(m.node()->InputAt(0));
if (m.IsBitcastTaggedSignedToWord()) {
Int64Matcher n(m.node()->InputAt(0));
if (n.IsChangeCompressedToTagged()) {
DCHECK(machine()->Is64() && SmiValuesAre31Bits());
return Replace(BitcastCompressedSignedToWord32(n.node()->InputAt(0)));
}
}
break;
}
case IrOpcode::kTruncateFloat64ToFloat32: {
@ -871,7 +885,6 @@ Reduction MachineOperatorReducer::ReduceInt32Div(Node* node) {
return NoChange();
}
Reduction MachineOperatorReducer::ReduceUint32Div(Node* node) {
Uint32BinopMatcher m(node);
if (m.left().Is(0)) return Replace(m.left().node()); // 0 / x => 0
@ -900,7 +913,6 @@ Reduction MachineOperatorReducer::ReduceUint32Div(Node* node) {
return NoChange();
}
Reduction MachineOperatorReducer::ReduceInt32Mod(Node* node) {
Int32BinopMatcher m(node);
if (m.left().Is(0)) return Replace(m.left().node()); // 0 % x => 0
@ -937,7 +949,6 @@ Reduction MachineOperatorReducer::ReduceInt32Mod(Node* node) {
return NoChange();
}
Reduction MachineOperatorReducer::ReduceUint32Mod(Node* node) {
Uint32BinopMatcher m(node);
if (m.left().Is(0)) return Replace(m.left().node()); // 0 % x => 0
@ -967,7 +978,6 @@ Reduction MachineOperatorReducer::ReduceUint32Mod(Node* node) {
return NoChange();
}
Reduction MachineOperatorReducer::ReduceStore(Node* node) {
NodeMatcher nm(node);
MachineRepresentation rep;
@ -1015,7 +1025,6 @@ Reduction MachineOperatorReducer::ReduceStore(Node* node) {
return NoChange();
}
Reduction MachineOperatorReducer::ReduceProjection(size_t index, Node* node) {
switch (node->opcode()) {
case IrOpcode::kInt32AddWithOverflow: {
@ -1069,7 +1078,6 @@ Reduction MachineOperatorReducer::ReduceProjection(size_t index, Node* node) {
return NoChange();
}
Reduction MachineOperatorReducer::ReduceWord32Shifts(Node* node) {
DCHECK((node->opcode() == IrOpcode::kWord32Shl) ||
(node->opcode() == IrOpcode::kWord32Shr) ||
@ -1089,7 +1097,6 @@ Reduction MachineOperatorReducer::ReduceWord32Shifts(Node* node) {
return NoChange();
}
Reduction MachineOperatorReducer::ReduceWord32Shl(Node* node) {
DCHECK_EQ(IrOpcode::kWord32Shl, node->opcode());
Int32BinopMatcher m(node);
@ -1399,7 +1406,6 @@ Reduction MachineOperatorReducer::ReduceFloat64InsertLowWord32(Node* node) {
return NoChange();
}
Reduction MachineOperatorReducer::ReduceFloat64InsertHighWord32(Node* node) {
DCHECK_EQ(IrOpcode::kFloat64InsertHighWord32, node->opcode());
Float64Matcher mlhs(node->InputAt(0));
@ -1412,7 +1418,6 @@ Reduction MachineOperatorReducer::ReduceFloat64InsertHighWord32(Node* node) {
return NoChange();
}
namespace {
bool IsFloat64RepresentableAsFloat32(const Float64Matcher& m) {
@ -1492,7 +1497,6 @@ CommonOperatorBuilder* MachineOperatorReducer::common() const {
return mcgraph()->common();
}
MachineOperatorBuilder* MachineOperatorReducer::machine() const {
return mcgraph()->machine();
}

2
src/compiler/machine-operator-reducer.h
View File

@ -51,6 +51,8 @@ class V8_EXPORT_PRIVATE MachineOperatorReducer final
Node* Word32Sar(Node* lhs, uint32_t rhs);
Node* Word32Shr(Node* lhs, uint32_t rhs);
Node* Word32Equal(Node* lhs, Node* rhs);
Node* BitcastWord32ToCompressedSigned(Node* value);
Node* BitcastCompressedSignedToWord32(Node* value);
Node* Int32Add(Node* lhs, Node* rhs);
Node* Int32Sub(Node* lhs, Node* rhs);
Node* Int32Mul(Node* lhs, Node* rhs);

2
src/compiler/machine-operator.cc
View File

@ -148,6 +148,8 @@ MachineType AtomicOpType(Operator const* op) {
V(Word64ReverseBytes, Operator::kNoProperties, 1, 0, 1) \
V(BitcastTaggedSignedToWord, Operator::kNoProperties, 1, 0, 1) \
V(BitcastWordToTaggedSigned, Operator::kNoProperties, 1, 0, 1) \
V(BitcastWord32ToCompressedSigned, Operator::kNoProperties, 1, 0, 1) \
V(BitcastCompressedSignedToWord32, Operator::kNoProperties, 1, 0, 1) \
V(TruncateFloat64ToWord32, Operator::kNoProperties, 1, 0, 1) \
V(ChangeFloat32ToFloat64, Operator::kNoProperties, 1, 0, 1) \
V(ChangeFloat64ToInt32, Operator::kNoProperties, 1, 0, 1) \

6
src/compiler/machine-operator.h
View File

@ -314,6 +314,12 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
// This operator reinterprets the bits of a word as a Smi.
const Operator* BitcastWordToTaggedSigned();
// This operator reinterprets the bits of a word32 as a Compressed Smi.
const Operator* BitcastWord32ToCompressedSigned();
// This operator reinterprets the bits of a Compressed Smi as a word32.
const Operator* BitcastCompressedSignedToWord32();
// JavaScript float64 to int32/uint32 truncation.
const Operator* TruncateFloat64ToWord32();

2
src/compiler/opcodes.h
View File

@ -674,6 +674,8 @@
V(BitcastTaggedSignedToWord) \
V(BitcastWordToTagged) \
V(BitcastWordToTaggedSigned) \
V(BitcastWord32ToCompressedSigned) \
V(BitcastCompressedSignedToWord32) \
V(TruncateFloat64ToWord32) \
V(ChangeFloat32ToFloat64) \
V(ChangeFloat64ToInt32) \

2
src/compiler/verifier.cc
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@ -1804,6 +1804,8 @@ void Verifier::Visitor::Check(Node* node, const AllNodes& all) {
case IrOpcode::kBitcastTaggedSignedToWord:
case IrOpcode::kBitcastWordToTagged:
case IrOpcode::kBitcastWordToTaggedSigned:
case IrOpcode::kBitcastWord32ToCompressedSigned:
case IrOpcode::kBitcastCompressedSignedToWord32:
case IrOpcode::kChangeInt32ToInt64:
case IrOpcode::kChangeUint32ToUint64:
case IrOpcode::kChangeTaggedToCompressed: