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ppc: [liftoff] fix shift op 2nd input overflow

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Change-Id: Idcb68ad86edbd1855c41532f776d0e7f42b7223b
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3097872
Reviewed-by: Milad Fa <mfarazma@redhat.com>
Commit-Queue: Junliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/master@{#76316}
This commit is contained in:
Junliang Yan 2021-08-16 10:47:52 -04:00 committed by V8 LUCI CQ
parent 22553aa4f8
commit 47bcce5b4b
1 changed files with 13 additions and 6 deletions
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19
src/wasm/baseline/ppc/liftoff-assembler-ppc.h
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@ -750,12 +750,19 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
#define SIGN_EXT(r) extsw(r, r)
#define ROUND_F64_TO_F32(fpr) frsp(fpr, fpr)
#define INT32_AND_WITH_1F(x) Operand(x & 0x1f)
#define INT32_AND_WITH_3F(x) Operand(x & 0x3f)
#define REGISTER_AND_WITH_1F \
([&](Register rhs) { \
andi(r0, rhs, Operand(31)); \
return r0; \
})
#define REGISTER_AND_WITH_3F \
([&](Register rhs) { \
andi(r0, rhs, Operand(63)); \
return r0; \
})
#define LFR_TO_REG(reg) reg.gp()
// V(name, instr, dtype, stype, dcast, scast, rcast, return_val, return_type)
@ -873,17 +880,17 @@ UNOP_LIST(EMIT_UNOP_FUNCTION)
V(i32_shr, ShiftRightU32, Register, Register, Register, , , \
REGISTER_AND_WITH_1F, USE, , void) \
V(i64_shl, ShiftLeftU64, LiftoffRegister, LiftoffRegister, Register, \
LFR_TO_REG, LFR_TO_REG, , USE, , void) \
LFR_TO_REG, LFR_TO_REG, REGISTER_AND_WITH_3F, USE, , void) \
V(i64_sar, ShiftRightS64, LiftoffRegister, LiftoffRegister, Register, \
LFR_TO_REG, LFR_TO_REG, , USE, , void) \
LFR_TO_REG, LFR_TO_REG, REGISTER_AND_WITH_3F, USE, , void) \
V(i64_shr, ShiftRightU64, LiftoffRegister, LiftoffRegister, Register, \
LFR_TO_REG, LFR_TO_REG, , USE, , void) \
LFR_TO_REG, LFR_TO_REG, REGISTER_AND_WITH_3F, USE, , void) \
V(i64_shli, ShiftLeftU64, LiftoffRegister, LiftoffRegister, int32_t, \
LFR_TO_REG, LFR_TO_REG, Operand, USE, , void) \
LFR_TO_REG, LFR_TO_REG, INT32_AND_WITH_3F, USE, , void) \
V(i64_sari, ShiftRightS64, LiftoffRegister, LiftoffRegister, int32_t, \
LFR_TO_REG, LFR_TO_REG, Operand, USE, , void) \
LFR_TO_REG, LFR_TO_REG, INT32_AND_WITH_3F, USE, , void) \
V(i64_shri, ShiftRightU64, LiftoffRegister, LiftoffRegister, int32_t, \
LFR_TO_REG, LFR_TO_REG, Operand, USE, , void) \
LFR_TO_REG, LFR_TO_REG, INT32_AND_WITH_3F, USE, , void) \
V(f64_add, AddF64, DoubleRegister, DoubleRegister, DoubleRegister, , , , \
USE, , void) \
V(f64_sub, SubF64, DoubleRegister, DoubleRegister, DoubleRegister, , , , \