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MIPS: Tiny improvement of register constraints in LClassOfTest instructions.

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Port r10379 (3399d6).

Original commit message:
The input register does not need to be made writable. We already
allocate enough temp registers and the input register will always
be preserved.

BUG=
TEST=
Review URL: http://codereview.chromium.org/9254025

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10437 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
fschneider@chromium.org 2012-01-19 13:07:46 +00:00
parent 5b81bd0f0c
commit 48a24b9224
2 changed files with 6 additions and 5 deletions
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9
src/mips/lithium-codegen-mips.cc
View File

@ -1862,9 +1862,8 @@ void LCodeGen::DoHasCachedArrayIndexAndBranch(
}
// Branches to a label or falls through with this instance class-name adr
// returned in temp reg, available for comparison by the caller. Trashes the
// temp registers, but not the input. Only input and temp2 may alias.
// Branches to a label or falls through with the answer in flags. Trashes
// the temp registers, but not the input.
void LCodeGen::EmitClassOfTest(Label* is_true,
Label* is_false,
Handle<String>class_name,
@ -1872,7 +1871,9 @@ void LCodeGen::EmitClassOfTest(Label* is_true,
Register temp,
Register temp2) {
ASSERT(!input.is(temp));
ASSERT(!temp.is(temp2)); // But input and temp2 may be the same register.
ASSERT(!input.is(temp2));
ASSERT(!temp.is(temp2));
__ JumpIfSmi(input, is_false);
if (class_name->IsEqualTo(CStrVector("Function"))) {

2
src/mips/lithium-mips.cc
View File

@ -1554,7 +1554,7 @@ LInstruction* LChunkBuilder::DoHasCachedArrayIndexAndBranch(
LInstruction* LChunkBuilder::DoClassOfTestAndBranch(
HClassOfTestAndBranch* instr) {
ASSERT(instr->value()->representation().IsTagged());
return new LClassOfTestAndBranch(UseTempRegister(instr->value()),
return new LClassOfTestAndBranch(UseRegister(instr->value()),
TempRegister());
}