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[mips][wasm-simd] Implement f64x2 min max

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port 91ee5f0 https://crrev.com/c/1925614

Original Commit Message:

 [wasm-simd] Implement f64x2 min max for arm

Change-Id: I41b350cdcc9242b2fed6260873dc202367509137
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1947690
Auto-Submit: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Reviewed-by: Bill Budge <bbudge@chromium.org>
Commit-Queue: Bill Budge <bbudge@chromium.org>
Cr-Commit-Position: refs/heads/master@{#65342}
This commit is contained in:
Zhao Jiazhong 2019-12-04 01:41:37 -05:00 committed by Commit Bot
parent 429701fd7a
commit 496adfceec
8 changed files with 32 additions and 0 deletions
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10
src/compiler/backend/mips/code-generator-mips.cc
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@ -1984,6 +1984,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fdiv_d);
break;
}
case kMipsF64x2Min: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fmin_d);
break;
}
case kMipsF64x2Max: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fmax_d);
break;
}
case kMipsF64x2Eq: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fceq_d(i.OutputSimd128Register(), i.InputSimd128Register(0),

2
src/compiler/backend/mips/instruction-codes-mips.h
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@ -149,6 +149,8 @@ namespace compiler {
V(MipsF64x2Sub) \
V(MipsF64x2Mul) \
V(MipsF64x2Div) \
V(MipsF64x2Min) \
V(MipsF64x2Max) \
V(MipsF64x2Eq) \
V(MipsF64x2Ne) \
V(MipsF64x2Lt) \

2
src/compiler/backend/mips/instruction-scheduler-mips.cc
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@ -48,6 +48,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsF64x2Sub:
case kMipsF64x2Mul:
case kMipsF64x2Div:
case kMipsF64x2Min:
case kMipsF64x2Max:
case kMipsF64x2Eq:
case kMipsF64x2Ne:
case kMipsF64x2Lt:

2
src/compiler/backend/mips/instruction-selector-mips.cc
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@ -2081,6 +2081,8 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F64x2Sub, kMipsF64x2Sub) \
V(F64x2Mul, kMipsF64x2Mul) \
V(F64x2Div, kMipsF64x2Div) \
V(F64x2Min, kMipsF64x2Min) \
V(F64x2Max, kMipsF64x2Max) \
V(F64x2Eq, kMipsF64x2Eq) \
V(F64x2Ne, kMipsF64x2Ne) \
V(F64x2Lt, kMipsF64x2Lt) \

10
src/compiler/backend/mips64/code-generator-mips64.cc
View File

@ -2099,6 +2099,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fdiv_d);
break;
}
case kMips64F64x2Min: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fmin_d);
break;
}
case kMips64F64x2Max: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fmax_d);
break;
}
case kMips64F64x2Eq: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fceq_d(i.OutputSimd128Register(), i.InputSimd128Register(0),

2
src/compiler/backend/mips64/instruction-codes-mips64.h
View File

@ -194,6 +194,8 @@ namespace compiler {
V(Mips64F64x2Sub) \
V(Mips64F64x2Mul) \
V(Mips64F64x2Div) \
V(Mips64F64x2Min) \
V(Mips64F64x2Max) \
V(Mips64F64x2Eq) \
V(Mips64F64x2Ne) \
V(Mips64F64x2Lt) \

2
src/compiler/backend/mips64/instruction-scheduler-mips64.cc
View File

@ -76,6 +76,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64F64x2Sub:
case kMips64F64x2Mul:
case kMips64F64x2Div:
case kMips64F64x2Min:
case kMips64F64x2Max:
case kMips64F64x2Eq:
case kMips64F64x2Ne:
case kMips64F64x2Lt:

2
src/compiler/backend/mips64/instruction-selector-mips64.cc
View File

@ -2752,6 +2752,8 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F64x2Sub, kMips64F64x2Sub) \
V(F64x2Mul, kMips64F64x2Mul) \
V(F64x2Div, kMips64F64x2Div) \
V(F64x2Min, kMips64F64x2Min) \
V(F64x2Max, kMips64F64x2Max) \
V(F64x2Eq, kMips64F64x2Eq) \
V(F64x2Ne, kMips64F64x2Ne) \
V(F64x2Lt, kMips64F64x2Lt) \