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[arm64][compiler] Instruction select add/sub sxtw

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Modify TryAnyExtendMatch to combine Int64Add/Int64Sub(x, ChangeInt32ToInt64(y))
to use an extend register operand, removing the cast.

Change-Id: Id130f8a9614e2c208f9ed8c17b923ee738fcb916
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2857964
Reviewed-by: Andreas Haas <ahaas@chromium.org>
Reviewed-by: Georg Neis <neis@chromium.org>
Commit-Queue: Martyn Capewell <martyn.capewell@arm.com>
Cr-Commit-Position: refs/heads/master@{#74285}
This commit is contained in:
Sam Parker 2021-04-29 11:25:52 +01:00 committed by V8 LUCI CQ
parent ad5f34a1d8
commit 4bd6f82cda
2 changed files with 21 additions and 0 deletions
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6
src/compiler/backend/arm64/instruction-selector-arm64.cc
View File

@ -354,6 +354,12 @@ bool TryMatchAnyExtend(Arm64OperandGenerator* g, InstructionSelector* selector,
return true;
}
}
} else if (nm.IsChangeInt32ToInt64()) {
// Use extended register form.
*opcode |= AddressingModeField::encode(kMode_Operand2_R_SXTW);
*left_op = g->UseRegister(left_node);
*right_op = g->UseRegister(right_node->InputAt(0));
return true;
}
return false;
}

15
test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc
View File

@ -642,6 +642,21 @@ TEST_P(InstructionSelectorAddSubTest, SignedExtendHalfword) {
ASSERT_EQ(1U, s[0]->OutputCount());
}
TEST_P(InstructionSelectorAddSubTest, SignedExtendWord) {
const AddSub dpi = GetParam();
const MachineType type = dpi.mi.machine_type;
if (type != MachineType::Int64()) return;
StreamBuilder m(this, type, type, type);
m.Return((m.*dpi.mi.constructor)(m.Parameter(0),
m.ChangeInt32ToInt64(m.Parameter(1))));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
EXPECT_EQ(dpi.mi.arch_opcode, s[0]->arch_opcode());
EXPECT_EQ(kMode_Operand2_R_SXTW, s[0]->addressing_mode());
ASSERT_EQ(2U, s[0]->InputCount());
ASSERT_EQ(1U, s[0]->OutputCount());
}
INSTANTIATE_TEST_SUITE_P(InstructionSelectorTest, InstructionSelectorAddSubTest,
::testing::ValuesIn(kAddSubInstructions));