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[mips][wasm-simd] Implement f64x2 comparisons

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port b6edadc https://crrev.com/c/1872930

Original Commit Message:

  [wasm-simd] Implement f64x2 comparisons for arm

Change-Id: If0fab2307a7f6da75f27ecd90cef6e15945214dd
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1903290
Reviewed-by: Bill Budge <bbudge@chromium.org>
Commit-Queue: Bill Budge <bbudge@chromium.org>
Auto-Submit: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Cr-Commit-Position: refs/heads/master@{#64868}
This commit is contained in:
Zhao Jiazhong 2019-11-07 22:49:23 -05:00 committed by Commit Bot
parent 6faaf4cc27
commit 4ec5b79ce2
8 changed files with 72 additions and 0 deletions
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24
src/compiler/backend/mips/code-generator-mips.cc
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@ -1984,6 +1984,30 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fdiv_d);
break;
}
case kMipsF64x2Eq: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fceq_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMipsF64x2Ne: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fcne_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMipsF64x2Lt: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fclt_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMipsF64x2Le: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fcle_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMipsF64x2Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register dst = i.OutputSimd128Register();

4
src/compiler/backend/mips/instruction-codes-mips.h
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@ -149,6 +149,10 @@ namespace compiler {
V(MipsF64x2Sub) \
V(MipsF64x2Mul) \
V(MipsF64x2Div) \
V(MipsF64x2Eq) \
V(MipsF64x2Ne) \
V(MipsF64x2Lt) \
V(MipsF64x2Le) \
V(MipsF32x4Splat) \
V(MipsF32x4ExtractLane) \
V(MipsF32x4ReplaceLane) \

4
src/compiler/backend/mips/instruction-scheduler-mips.cc
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@ -48,6 +48,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsF64x2Sub:
case kMipsF64x2Mul:
case kMipsF64x2Div:
case kMipsF64x2Eq:
case kMipsF64x2Ne:
case kMipsF64x2Lt:
case kMipsF64x2Le:
case kMipsF64x2Splat:
case kMipsF64x2ExtractLane:
case kMipsF64x2ReplaceLane:

4
src/compiler/backend/mips/instruction-selector-mips.cc
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@ -2081,6 +2081,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F64x2Sub, kMipsF64x2Sub) \
V(F64x2Mul, kMipsF64x2Mul) \
V(F64x2Div, kMipsF64x2Div) \
V(F64x2Eq, kMipsF64x2Eq) \
V(F64x2Ne, kMipsF64x2Ne) \
V(F64x2Lt, kMipsF64x2Lt) \
V(F64x2Le, kMipsF64x2Le) \
V(F32x4Add, kMipsF32x4Add) \
V(F32x4AddHoriz, kMipsF32x4AddHoriz) \
V(F32x4Sub, kMipsF32x4Sub) \

24
src/compiler/backend/mips64/code-generator-mips64.cc
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@ -2099,6 +2099,30 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fdiv_d);
break;
}
case kMips64F64x2Eq: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fceq_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMips64F64x2Ne: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fcne_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMips64F64x2Lt: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fclt_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMips64F64x2Le: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fcle_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMips64F64x2Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ Move(kScratchReg, i.InputDoubleRegister(0));

4
src/compiler/backend/mips64/instruction-codes-mips64.h
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@ -194,6 +194,10 @@ namespace compiler {
V(Mips64F64x2Sub) \
V(Mips64F64x2Mul) \
V(Mips64F64x2Div) \
V(Mips64F64x2Eq) \
V(Mips64F64x2Ne) \
V(Mips64F64x2Lt) \
V(Mips64F64x2Le) \
V(Mips64F64x2Splat) \
V(Mips64F64x2ExtractLane) \
V(Mips64F64x2ReplaceLane) \

4
src/compiler/backend/mips64/instruction-scheduler-mips64.cc
View File

@ -76,6 +76,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64F64x2Sub:
case kMips64F64x2Mul:
case kMips64F64x2Div:
case kMips64F64x2Eq:
case kMips64F64x2Ne:
case kMips64F64x2Lt:
case kMips64F64x2Le:
case kMips64F32x4Abs:
case kMips64F32x4Add:
case kMips64F32x4AddHoriz:

4
src/compiler/backend/mips64/instruction-selector-mips64.cc
View File

@ -2744,6 +2744,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F64x2Sub, kMips64F64x2Sub) \
V(F64x2Mul, kMips64F64x2Mul) \
V(F64x2Div, kMips64F64x2Div) \
V(F64x2Eq, kMips64F64x2Eq) \
V(F64x2Ne, kMips64F64x2Ne) \
V(F64x2Lt, kMips64F64x2Lt) \
V(F64x2Le, kMips64F64x2Le) \
V(F32x4Add, kMips64F32x4Add) \
V(F32x4AddHoriz, kMips64F32x4AddHoriz) \
V(F32x4Sub, kMips64F32x4Sub) \