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Revert "[wasm-simd][x64] Optimize pmin/pmax and add horiz for AVX"

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This reverts commit 3c4e434f0c.

Reason for revert: Fails noavx tests: https://ci.chromium.org/p/v8/builders/ci/V8%20Linux64%20-%20debug/34613

Original change's description:
> [wasm-simd][x64] Optimize pmin/pmax and add horiz for AVX
>
> The AVX versions of these instructions can take 3 operands, so we don't
> need to force dst == src.
>
> Bug: v8:9561
> Change-Id: If346a05f7d599bf0d636263cafc3bc823c3b8452
> Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2515337
> Reviewed-by: Clemens Backes <clemensb@chromium.org>
> Commit-Queue: Zhi An Ng <zhin@chromium.org>
> Cr-Commit-Position: refs/heads/master@{#70958}

TBR=clemensb@chromium.org,zhin@chromium.org

Change-Id: I5fcdd2e51d418cb32a1b1e2bec7c0dff19f29154
No-Presubmit: true
No-Tree-Checks: true
No-Try: true
Bug: v8:9561
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2519558
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/master@{#70961}
This commit is contained in:
Clemens Backes 2020-11-04 11:15:03 +00:00 committed by Commit Bot
parent ccce6f2a59
commit 4f4dda3f84
2 changed files with 17 additions and 10 deletions
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19
src/compiler/backend/x64/code-generator-x64.cc
View File

@ -2582,7 +2582,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kX64F32x4AddHoriz: {
ASSEMBLE_SIMD_BINOP(haddps);
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ Haddps(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64F32x4Sub: {
@ -2679,11 +2680,15 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kX64F32x4Pmin: {
ASSEMBLE_SIMD_BINOP(minps);
XMMRegister dst = i.OutputSimd128Register();
DCHECK_EQ(dst, i.InputSimd128Register(0));
__ Minps(dst, i.InputSimd128Register(1));
break;
}
case kX64F32x4Pmax: {
ASSEMBLE_SIMD_BINOP(maxps);
XMMRegister dst = i.OutputSimd128Register();
DCHECK_EQ(dst, i.InputSimd128Register(0));
__ Maxps(dst, i.InputSimd128Register(1));
break;
}
case kX64F32x4Round: {
@ -2699,11 +2704,15 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kX64F64x2Pmin: {
ASSEMBLE_SIMD_BINOP(minpd);
XMMRegister dst = i.OutputSimd128Register();
DCHECK_EQ(dst, i.InputSimd128Register(0));
__ Minpd(dst, i.InputSimd128Register(1));
break;
}
case kX64F64x2Pmax: {
ASSEMBLE_SIMD_BINOP(maxpd);
XMMRegister dst = i.OutputSimd128Register();
DCHECK_EQ(dst, i.InputSimd128Register(0));
__ Maxpd(dst, i.InputSimd128Register(1));
break;
}
case kX64I64x2Splat: {

8
src/compiler/backend/x64/instruction-selector-x64.cc
View File

@ -2810,7 +2810,6 @@ VISIT_ATOMIC_BINOP(Xor)
V(F64x2Lt) \
V(F64x2Le) \
V(F32x4Add) \
V(F32x4AddHoriz) \
V(F32x4Sub) \
V(F32x4Mul) \
V(F32x4Div) \
@ -2871,6 +2870,7 @@ VISIT_ATOMIC_BINOP(Xor)
#define SIMD_BINOP_LIST(V) \
V(F64x2Min) \
V(F64x2Max) \
V(F32x4AddHoriz) \
V(F32x4Min) \
V(F32x4Max) \
V(I32x4GeS) \
@ -3575,10 +3575,8 @@ void VisitPminOrPmax(InstructionSelector* selector, Node* node,
// Due to the way minps/minpd work, we want the dst to be same as the second
// input: b = pmin(a, b) directly maps to minps b a.
X64OperandGenerator g(selector);
InstructionOperand dst = selector->IsSupported(AVX)
? g.DefineAsRegister(node)
: g.DefineSameAsFirst(node);
selector->Emit(opcode, dst, g.UseRegister(node->InputAt(1)),
selector->Emit(opcode, g.DefineSameAsFirst(node),
g.UseRegister(node->InputAt(1)),
g.UseRegister(node->InputAt(0)));
}
} // namespace