[test] make instruction sequence test emit cfgs more like the scheduler

BUG=

Review URL: https://codereview.chromium.org/1116923002

Cr-Commit-Position: refs/heads/master@{#28167}
This commit is contained in:
dcarney 2015-04-30 06:39:11 -07:00 committed by Commit bot
parent 1621dbf370
commit 4fe546c785
2 changed files with 17 additions and 4 deletions

View File

@ -109,7 +109,7 @@ Instruction* InstructionSequenceTest::EndBlock(BlockCompletion completion) {
case kBlockEnd:
break;
case kFallThrough:
result = EmitFallThrough();
result = EmitJump();
break;
case kJump:
CHECK(!block_returns_);
@ -441,11 +441,20 @@ InstructionBlock* InstructionSequenceTest::NewBlock() {
void InstructionSequenceTest::WireBlocks() {
CHECK(!current_block());
CHECK(instruction_blocks_.size() == completions_.size());
CHECK(loop_blocks_.empty());
// Wire in end block to look like a scheduler produced cfg.
auto end_block = NewBlock();
current_block_ = nullptr;
sequence()->EndBlock(end_block->rpo_number());
size_t offset = 0;
for (const auto& completion : completions_) {
switch (completion.type_) {
case kBlockEnd:
case kBlockEnd: {
auto block = instruction_blocks_[offset];
block->successors().push_back(end_block->rpo_number());
end_block->predecessors().push_back(block->rpo_number());
break;
}
case kFallThrough: // Fallthrough.
case kJump:
WireBlock(offset, completion.offset_0_);

View File

@ -136,9 +136,11 @@ TEST_F(MoveOptimizerTest, SimpleMerge) {
StartBlock();
EndBlock(Last());
auto last = LastInstruction();
Optimize();
auto move = LastInstruction()->parallel_moves()[0];
auto move = last->parallel_moves()[0];
CHECK_EQ(1, NonRedundantSize(move));
CHECK(Contains(move, Reg(0), Reg(1)));
}
@ -163,11 +165,13 @@ TEST_F(MoveOptimizerTest, SimpleMergeCycle) {
StartBlock();
EndBlock(Last());
auto last = LastInstruction();
Optimize();
CHECK(gap_0->AreMovesRedundant());
CHECK(gap_1->AreMovesRedundant());
auto move = LastInstruction()->parallel_moves()[0];
auto move = last->parallel_moves()[0];
CHECK_EQ(2, NonRedundantSize(move));
CHECK(Contains(move, Reg(0), Reg(1)));
CHECK(Contains(move, Reg(1), Reg(0)));