MIPS: Port for (fused) multiply add/subtract.
Port for VisitFloat32Add, VisitFloat64Add, VisitFloat32Sub and
VisitFloat64Sub in InstructionSelector.
TEST=unittests/InstructionSelectorTest.Float32AddWithFloat32Mul,
unittests/InstructionSelectorTest.Float64AddWithFloat64Mul,
unittests/InstructionSelectorTest.Float32SubWithFloat32Mul,
unittests/InstructionSelectorTest.Float64SubWithFloat64Mul
BUG=
Review-Url: https://codereview.chromium.org/2341303002
Cr-Commit-Position: refs/heads/master@{#39616}
This commit is contained in:
Ilija.Pavlovic
Commit bot
parent
154548c2ba
commit
502b9aa71b
@ -1118,6 +1118,38 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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__ sub_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
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i.InputDoubleRegister(1));
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break;
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case kMipsMaddS:
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__ madd_s(i.OutputFloatRegister(), i.InputFloatRegister(0),
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i.InputFloatRegister(1), i.InputFloatRegister(2));
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break;
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case kMipsMaddD:
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__ madd_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
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i.InputDoubleRegister(1), i.InputDoubleRegister(2));
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break;
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case kMipsMaddfS:
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__ maddf_s(i.OutputFloatRegister(), i.InputFloatRegister(1),
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i.InputFloatRegister(2));
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break;
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case kMipsMaddfD:
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__ maddf_d(i.OutputDoubleRegister(), i.InputDoubleRegister(1),
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i.InputDoubleRegister(2));
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break;
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case kMipsMsubS:
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__ msub_s(i.OutputFloatRegister(), i.InputFloatRegister(0),
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i.InputFloatRegister(1), i.InputFloatRegister(2));
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break;
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case kMipsMsubD:
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__ msub_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
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i.InputDoubleRegister(1), i.InputDoubleRegister(2));
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break;
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case kMipsMsubfS:
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__ msubf_s(i.OutputFloatRegister(), i.InputFloatRegister(1),
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i.InputFloatRegister(2));
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break;
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case kMipsMsubfD:
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__ msubf_d(i.OutputDoubleRegister(), i.InputDoubleRegister(1),
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i.InputDoubleRegister(2));
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break;
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case kMipsMulD:
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// TODO(plind): add special case: right op is -1.0, see arm port.
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__ mul_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
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@ -69,6 +69,14 @@ namespace compiler {
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V(MipsAddPair) \
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V(MipsSubPair) \
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V(MipsMulPair) \
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V(MipsMaddS) \
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V(MipsMaddD) \
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V(MipsMaddfS) \
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V(MipsMaddfD) \
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V(MipsMsubS) \
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V(MipsMsubD) \
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V(MipsMsubfS) \
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V(MipsMsubfD) \
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V(MipsFloat32RoundDown) \
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V(MipsFloat32RoundTruncate) \
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V(MipsFloat32RoundUp) \
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@ -781,20 +781,126 @@ void InstructionSelector::VisitBitcastInt32ToFloat32(Node* node) {
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void InstructionSelector::VisitFloat32Add(Node* node) {
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MipsOperandGenerator g(this);
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Float32BinopMatcher m(node);
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if (m.left().IsFloat32Mul() && CanCover(node, m.left().node())) {
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// For Add.S(Mul.S(x, y), z):
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Float32BinopMatcher mleft(m.left().node());
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if (IsMipsArchVariant(kMips32r2)) { // Select Madd.S(z, x, y).
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Emit(kMipsMaddS, g.DefineAsRegister(node),
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g.UseRegister(m.right().node()), g.UseRegister(mleft.left().node()),
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g.UseRegister(mleft.right().node()));
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return;
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} else if (IsMipsArchVariant(kMips32r6)) { // Select Maddf.S(z, x, y).
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Emit(kMipsMaddfS, g.DefineSameAsFirst(node),
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g.UseRegister(m.right().node()), g.UseRegister(mleft.left().node()),
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g.UseRegister(mleft.right().node()));
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return;
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}
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}
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if (m.right().IsFloat32Mul() && CanCover(node, m.right().node())) {
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// For Add.S(x, Mul.S(y, z)):
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Float32BinopMatcher mright(m.right().node());
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if (IsMipsArchVariant(kMips32r2)) { // Select Madd.S(x, y, z).
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Emit(kMipsMaddS, g.DefineAsRegister(node), g.UseRegister(m.left().node()),
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g.UseRegister(mright.left().node()),
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g.UseRegister(mright.right().node()));
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return;
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} else if (IsMipsArchVariant(kMips32r6)) { // Select Maddf.S(x, y, z).
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Emit(kMipsMaddfS, g.DefineSameAsFirst(node),
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g.UseRegister(m.left().node()), g.UseRegister(mright.left().node()),
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g.UseRegister(mright.right().node()));
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return;
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}
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}
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VisitRRR(this, kMipsAddS, node);
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}
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void InstructionSelector::VisitFloat64Add(Node* node) {
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MipsOperandGenerator g(this);
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Float64BinopMatcher m(node);
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if (m.left().IsFloat64Mul() && CanCover(node, m.left().node())) {
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// For Add.D(Mul.D(x, y), z):
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Float64BinopMatcher mleft(m.left().node());
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if (IsMipsArchVariant(kMips32r2)) { // Select Madd.D(z, x, y).
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Emit(kMipsMaddD, g.DefineAsRegister(node),
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g.UseRegister(m.right().node()), g.UseRegister(mleft.left().node()),
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g.UseRegister(mleft.right().node()));
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return;
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} else if (IsMipsArchVariant(kMips32r6)) { // Select Maddf.D(z, x, y).
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Emit(kMipsMaddfD, g.DefineSameAsFirst(node),
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g.UseRegister(m.right().node()), g.UseRegister(mleft.left().node()),
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g.UseRegister(mleft.right().node()));
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return;
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}
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}
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if (m.right().IsFloat64Mul() && CanCover(node, m.right().node())) {
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// For Add.D(x, Mul.D(y, z)):
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Float64BinopMatcher mright(m.right().node());
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if (IsMipsArchVariant(kMips32r2)) { // Select Madd.D(x, y, z).
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Emit(kMipsMaddD, g.DefineAsRegister(node), g.UseRegister(m.left().node()),
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g.UseRegister(mright.left().node()),
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g.UseRegister(mright.right().node()));
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return;
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} else if (IsMipsArchVariant(kMips32r6)) { // Select Maddf.D(x, y, z).
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Emit(kMipsMaddfD, g.DefineSameAsFirst(node),
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g.UseRegister(m.left().node()), g.UseRegister(mright.left().node()),
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g.UseRegister(mright.right().node()));
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return;
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}
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}
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VisitRRR(this, kMipsAddD, node);
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}
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void InstructionSelector::VisitFloat32Sub(Node* node) {
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MipsOperandGenerator g(this);
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Float32BinopMatcher m(node);
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if (m.left().IsFloat32Mul() && CanCover(node, m.left().node())) {
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if (IsMipsArchVariant(kMips32r2)) {
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// For Sub.S(Mul.S(x,y), z) select Msub.S(z, x, y).
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Float32BinopMatcher mleft(m.left().node());
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Emit(kMipsMsubS, g.DefineAsRegister(node),
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g.UseRegister(m.right().node()), g.UseRegister(mleft.left().node()),
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g.UseRegister(mleft.right().node()));
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return;
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}
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} else if (m.right().IsFloat32Mul() && CanCover(node, m.right().node())) {
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if (IsMipsArchVariant(kMips32r6)) {
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// For Sub.S(x,Mul.S(y,z)) select Msubf.S(x, y, z).
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Float32BinopMatcher mright(m.right().node());
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Emit(kMipsMsubfS, g.DefineSameAsFirst(node),
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g.UseRegister(m.left().node()), g.UseRegister(mright.left().node()),
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g.UseRegister(mright.right().node()));
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return;
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}
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}
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VisitRRR(this, kMipsSubS, node);
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}
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void InstructionSelector::VisitFloat64Sub(Node* node) {
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MipsOperandGenerator g(this);
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Float64BinopMatcher m(node);
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if (m.left().IsFloat64Mul() && CanCover(node, m.left().node())) {
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if (IsMipsArchVariant(kMips32r2)) {
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// For Sub.D(Mul.S(x,y), z) select Msub.D(z, x, y).
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Float64BinopMatcher mleft(m.left().node());
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Emit(kMipsMsubD, g.DefineAsRegister(node),
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g.UseRegister(m.right().node()), g.UseRegister(mleft.left().node()),
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g.UseRegister(mleft.right().node()));
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return;
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}
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} else if (m.right().IsFloat64Mul() && CanCover(node, m.right().node())) {
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if (IsMipsArchVariant(kMips32r6)) {
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// For Sub.D(x,Mul.S(y,z)) select Msubf.D(x, y, z).
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Float64BinopMatcher mright(m.right().node());
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Emit(kMipsMsubfD, g.DefineSameAsFirst(node),
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g.UseRegister(m.left().node()), g.UseRegister(mright.left().node()),
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g.UseRegister(mright.right().node()));
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return;
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}
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}
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VisitRRR(this, kMipsSubD, node);
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}
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@ -1314,6 +1314,38 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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__ sub_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
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i.InputDoubleRegister(1));
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break;
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case kMips64MaddS:
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__ madd_s(i.OutputFloatRegister(), i.InputFloatRegister(0),
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i.InputFloatRegister(1), i.InputFloatRegister(2));
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break;
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case kMips64MaddD:
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__ madd_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
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i.InputDoubleRegister(1), i.InputDoubleRegister(2));
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break;
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case kMips64MaddfS:
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__ maddf_s(i.OutputFloatRegister(), i.InputFloatRegister(1),
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i.InputFloatRegister(2));
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break;
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case kMips64MaddfD:
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__ maddf_d(i.OutputDoubleRegister(), i.InputDoubleRegister(1),
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i.InputDoubleRegister(2));
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break;
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case kMips64MsubS:
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__ msub_s(i.OutputFloatRegister(), i.InputFloatRegister(0),
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i.InputFloatRegister(1), i.InputFloatRegister(2));
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break;
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case kMips64MsubD:
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__ msub_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
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i.InputDoubleRegister(1), i.InputDoubleRegister(2));
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break;
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case kMips64MsubfS:
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__ msubf_s(i.OutputFloatRegister(), i.InputFloatRegister(1),
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i.InputFloatRegister(2));
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break;
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case kMips64MsubfD:
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__ msubf_d(i.OutputDoubleRegister(), i.InputDoubleRegister(1),
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i.InputDoubleRegister(2));
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break;
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case kMips64MulD:
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// TODO(plind): add special case: right op is -1.0, see arm port.
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__ mul_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
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@ -85,6 +85,14 @@ namespace compiler {
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V(Mips64SqrtD) \
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V(Mips64MaxD) \
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V(Mips64MinD) \
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V(Mips64MaddS) \
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V(Mips64MaddD) \
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V(Mips64MaddfS) \
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V(Mips64MaddfD) \
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V(Mips64MsubS) \
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V(Mips64MsubD) \
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V(Mips64MsubfS) \
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V(Mips64MsubfD) \
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V(Mips64Float64RoundDown) \
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V(Mips64Float64RoundTruncate) \
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V(Mips64Float64RoundUp) \
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@ -1224,20 +1224,126 @@ void InstructionSelector::VisitBitcastInt64ToFloat64(Node* node) {
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void InstructionSelector::VisitFloat32Add(Node* node) {
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Mips64OperandGenerator g(this);
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Float32BinopMatcher m(node);
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if (m.left().IsFloat32Mul() && CanCover(node, m.left().node())) {
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// For Add.S(Mul.S(x, y), z):
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Float32BinopMatcher mleft(m.left().node());
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if (kArchVariant == kMips64r2) { // Select Madd.S(z, x, y).
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Emit(kMips64MaddS, g.DefineAsRegister(node),
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g.UseRegister(m.right().node()), g.UseRegister(mleft.left().node()),
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g.UseRegister(mleft.right().node()));
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return;
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} else if (kArchVariant == kMips64r6) { // Select Maddf.S(z, x, y).
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Emit(kMips64MaddfS, g.DefineSameAsFirst(node),
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g.UseRegister(m.right().node()), g.UseRegister(mleft.left().node()),
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g.UseRegister(mleft.right().node()));
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return;
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}
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}
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if (m.right().IsFloat32Mul() && CanCover(node, m.right().node())) {
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// For Add.S(x, Mul.S(y, z)):
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Float32BinopMatcher mright(m.right().node());
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if (kArchVariant == kMips64r2) { // Select Madd.S(x, y, z).
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Emit(kMips64MaddS, g.DefineAsRegister(node),
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g.UseRegister(m.left().node()), g.UseRegister(mright.left().node()),
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g.UseRegister(mright.right().node()));
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return;
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} else if (kArchVariant == kMips64r6) { // Select Maddf.S(x, y, z).
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Emit(kMips64MaddfS, g.DefineSameAsFirst(node),
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g.UseRegister(m.left().node()), g.UseRegister(mright.left().node()),
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g.UseRegister(mright.right().node()));
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return;
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}
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}
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VisitRRR(this, kMips64AddS, node);
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}
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void InstructionSelector::VisitFloat64Add(Node* node) {
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Mips64OperandGenerator g(this);
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Float64BinopMatcher m(node);
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if (m.left().IsFloat64Mul() && CanCover(node, m.left().node())) {
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// For Add.D(Mul.D(x, y), z):
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Float64BinopMatcher mleft(m.left().node());
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if (kArchVariant == kMips64r2) { // Select Madd.D(z, x, y).
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Emit(kMips64MaddD, g.DefineAsRegister(node),
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g.UseRegister(m.right().node()), g.UseRegister(mleft.left().node()),
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g.UseRegister(mleft.right().node()));
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return;
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} else if (kArchVariant == kMips64r6) { // Select Maddf.D(z, x, y).
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Emit(kMips64MaddfD, g.DefineSameAsFirst(node),
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g.UseRegister(m.right().node()), g.UseRegister(mleft.left().node()),
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g.UseRegister(mleft.right().node()));
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return;
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}
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}
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if (m.right().IsFloat64Mul() && CanCover(node, m.right().node())) {
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// For Add.D(x, Mul.D(y, z)):
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Float64BinopMatcher mright(m.right().node());
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if (kArchVariant == kMips64r2) { // Select Madd.D(x, y, z).
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Emit(kMips64MaddD, g.DefineAsRegister(node),
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g.UseRegister(m.left().node()), g.UseRegister(mright.left().node()),
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g.UseRegister(mright.right().node()));
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return;
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} else if (kArchVariant == kMips64r6) { // Select Maddf.D(x, y, z).
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Emit(kMips64MaddfD, g.DefineSameAsFirst(node),
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g.UseRegister(m.left().node()), g.UseRegister(mright.left().node()),
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g.UseRegister(mright.right().node()));
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return;
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}
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}
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VisitRRR(this, kMips64AddD, node);
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}
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void InstructionSelector::VisitFloat32Sub(Node* node) {
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Mips64OperandGenerator g(this);
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Float32BinopMatcher m(node);
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if (m.left().IsFloat32Mul() && CanCover(node, m.left().node())) {
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if (kArchVariant == kMips64r2) {
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// For Sub.S(Mul.S(x,y), z) select Msub.S(z, x, y).
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Float32BinopMatcher mleft(m.left().node());
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Emit(kMips64MsubS, g.DefineAsRegister(node),
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g.UseRegister(m.right().node()), g.UseRegister(mleft.left().node()),
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g.UseRegister(mleft.right().node()));
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return;
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}
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} else if (m.right().IsFloat32Mul() && CanCover(node, m.right().node())) {
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if (kArchVariant == kMips64r6) {
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// For Sub.S(x,Mul.S(y,z)) select Msubf.S(x, y, z).
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Float32BinopMatcher mright(m.right().node());
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Emit(kMips64MsubfS, g.DefineSameAsFirst(node),
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g.UseRegister(m.left().node()), g.UseRegister(mright.left().node()),
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g.UseRegister(mright.right().node()));
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return;
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}
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}
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VisitRRR(this, kMips64SubS, node);
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}
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void InstructionSelector::VisitFloat64Sub(Node* node) {
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Mips64OperandGenerator g(this);
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Float64BinopMatcher m(node);
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if (m.left().IsFloat64Mul() && CanCover(node, m.left().node())) {
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if (kArchVariant == kMips64r2) {
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// For Sub.D(Mul.S(x,y), z) select Msub.D(z, x, y).
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Float64BinopMatcher mleft(m.left().node());
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Emit(kMips64MsubD, g.DefineAsRegister(node),
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g.UseRegister(m.right().node()), g.UseRegister(mleft.left().node()),
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g.UseRegister(mleft.right().node()));
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return;
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}
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} else if (m.right().IsFloat64Mul() && CanCover(node, m.right().node())) {
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if (kArchVariant == kMips64r6) {
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// For Sub.D(x,Mul.S(y,z)) select Msubf.D(x, y, z).
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Float64BinopMatcher mright(m.right().node());
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Emit(kMips64MsubfD, g.DefineSameAsFirst(node),
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g.UseRegister(m.left().node()), g.UseRegister(mright.left().node()),
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g.UseRegister(mright.right().node()));
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return;
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}
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}
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VisitRRR(this, kMips64SubD, node);
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}
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@ -1179,6 +1179,203 @@ TEST_F(InstructionSelectorTest, Float64Abs) {
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EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
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}
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|
||||
TEST_F(InstructionSelectorTest, Float32AddWithFloat32Mul) {
|
||||
{
|
||||
StreamBuilder m(this, MachineType::Float32(), MachineType::Float32(),
|
||||
MachineType::Float32(), MachineType::Float32());
|
||||
Node* const p0 = m.Parameter(0);
|
||||
Node* const p1 = m.Parameter(1);
|
||||
Node* const p2 = m.Parameter(2);
|
||||
Node* const n = m.Float32Add(m.Float32Mul(p0, p1), p2);
|
||||
m.Return(n);
|
||||
Stream s = m.Build();
|
||||
ASSERT_EQ(1U, s.size());
|
||||
if (IsMipsArchVariant(kMips32r2)) {
|
||||
EXPECT_EQ(kMipsMaddS, s[0]->arch_opcode());
|
||||
} else if (IsMipsArchVariant(kMips32r6)) {
|
||||
EXPECT_EQ(kMipsMaddfS, s[0]->arch_opcode());
|
||||
}
|
||||
ASSERT_EQ(3U, s[0]->InputCount());
|
||||
EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(0)));
|
||||
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(1)));
|
||||
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(2)));
|
||||
ASSERT_EQ(1U, s[0]->OutputCount());
|
||||
if (IsMipsArchVariant(kMips32r2)) {
|
||||
EXPECT_FALSE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
} else if (IsMipsArchVariant(kMips32r6)) {
|
||||
EXPECT_TRUE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
}
|
||||
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
||||
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
||||
}
|
||||
{
|
||||
StreamBuilder m(this, MachineType::Float32(), MachineType::Float32(),
|
||||
MachineType::Float32(), MachineType::Float32());
|
||||
Node* const p0 = m.Parameter(0);
|
||||
Node* const p1 = m.Parameter(1);
|
||||
Node* const p2 = m.Parameter(2);
|
||||
Node* const n = m.Float32Add(p0, m.Float32Mul(p1, p2));
|
||||
m.Return(n);
|
||||
Stream s = m.Build();
|
||||
ASSERT_EQ(1U, s.size());
|
||||
if (IsMipsArchVariant(kMips32r2)) {
|
||||
EXPECT_EQ(kMipsMaddS, s[0]->arch_opcode());
|
||||
} else if (IsMipsArchVariant(kMips32r6)) {
|
||||
EXPECT_EQ(kMipsMaddfS, s[0]->arch_opcode());
|
||||
}
|
||||
ASSERT_EQ(3U, s[0]->InputCount());
|
||||
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
||||
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
||||
EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2)));
|
||||
ASSERT_EQ(1U, s[0]->OutputCount());
|
||||
if (IsMipsArchVariant(kMips32r2)) {
|
||||
EXPECT_FALSE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
} else if (IsMipsArchVariant(kMips32r6)) {
|
||||
EXPECT_TRUE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
}
|
||||
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
||||
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
||||
}
|
||||
}
|
||||
|
||||
TEST_F(InstructionSelectorTest, Float64AddWithFloat64Mul) {
|
||||
{
|
||||
StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(),
|
||||
MachineType::Float64(), MachineType::Float64());
|
||||
Node* const p0 = m.Parameter(0);
|
||||
Node* const p1 = m.Parameter(1);
|
||||
Node* const p2 = m.Parameter(2);
|
||||
Node* const n = m.Float64Add(m.Float64Mul(p0, p1), p2);
|
||||
m.Return(n);
|
||||
Stream s = m.Build();
|
||||
ASSERT_EQ(1U, s.size());
|
||||
if (IsMipsArchVariant(kMips32r2)) {
|
||||
EXPECT_EQ(kMipsMaddD, s[0]->arch_opcode());
|
||||
} else if (IsMipsArchVariant(kMips32r6)) {
|
||||
EXPECT_EQ(kMipsMaddfD, s[0]->arch_opcode());
|
||||
}
|
||||
ASSERT_EQ(3U, s[0]->InputCount());
|
||||
EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(0)));
|
||||
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(1)));
|
||||
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(2)));
|
||||
ASSERT_EQ(1U, s[0]->OutputCount());
|
||||
if (IsMipsArchVariant(kMips32r2)) {
|
||||
EXPECT_FALSE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
} else if (IsMipsArchVariant(kMips32r6)) {
|
||||
EXPECT_TRUE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
}
|
||||
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
||||
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
||||
}
|
||||
{
|
||||
StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(),
|
||||
MachineType::Float64(), MachineType::Float64());
|
||||
Node* const p0 = m.Parameter(0);
|
||||
Node* const p1 = m.Parameter(1);
|
||||
Node* const p2 = m.Parameter(2);
|
||||
Node* const n = m.Float64Add(p0, m.Float64Mul(p1, p2));
|
||||
m.Return(n);
|
||||
Stream s = m.Build();
|
||||
ASSERT_EQ(1U, s.size());
|
||||
if (IsMipsArchVariant(kMips32r2)) {
|
||||
EXPECT_EQ(kMipsMaddD, s[0]->arch_opcode());
|
||||
} else if (IsMipsArchVariant(kMips32r6)) {
|
||||
EXPECT_EQ(kMipsMaddfD, s[0]->arch_opcode());
|
||||
}
|
||||
ASSERT_EQ(3U, s[0]->InputCount());
|
||||
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
||||
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
||||
EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2)));
|
||||
ASSERT_EQ(1U, s[0]->OutputCount());
|
||||
if (IsMipsArchVariant(kMips32r2)) {
|
||||
EXPECT_FALSE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
} else if (IsMipsArchVariant(kMips32r6)) {
|
||||
EXPECT_TRUE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
}
|
||||
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
||||
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
||||
}
|
||||
}
|
||||
|
||||
TEST_F(InstructionSelectorTest, Float32SubWithFloat32Mul) {
|
||||
StreamBuilder m(this, MachineType::Float32(), MachineType::Float32(),
|
||||
MachineType::Float32(), MachineType::Float32());
|
||||
Node* const p0 = m.Parameter(0);
|
||||
Node* const p1 = m.Parameter(1);
|
||||
Node* const p2 = m.Parameter(2);
|
||||
Node* n;
|
||||
if (IsMipsArchVariant(kMips32r2)) {
|
||||
n = m.Float32Sub(m.Float32Mul(p1, p2), p0);
|
||||
} else if (IsMipsArchVariant(kMips32r6)) {
|
||||
n = m.Float32Sub(p0, m.Float32Mul(p1, p2));
|
||||
}
|
||||
m.Return(n);
|
||||
Stream s = m.Build();
|
||||
ASSERT_EQ(1U, s.size());
|
||||
if (IsMipsArchVariant(kMips32r2)) {
|
||||
EXPECT_EQ(kMipsMsubS, s[0]->arch_opcode());
|
||||
} else if (IsMipsArchVariant(kMips32r6)) {
|
||||
EXPECT_EQ(kMipsMsubfS, s[0]->arch_opcode());
|
||||
}
|
||||
ASSERT_EQ(3U, s[0]->InputCount());
|
||||
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
||||
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
||||
EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2)));
|
||||
ASSERT_EQ(1U, s[0]->OutputCount());
|
||||
if (IsMipsArchVariant(kMips32r2)) {
|
||||
EXPECT_FALSE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
} else if (IsMipsArchVariant(kMips32r6)) {
|
||||
EXPECT_TRUE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
}
|
||||
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
||||
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
||||
}
|
||||
|
||||
TEST_F(InstructionSelectorTest, Float64SubWithFloat64Mul) {
|
||||
StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(),
|
||||
MachineType::Float64(), MachineType::Float64());
|
||||
Node* const p0 = m.Parameter(0);
|
||||
Node* const p1 = m.Parameter(1);
|
||||
Node* const p2 = m.Parameter(2);
|
||||
Node* n;
|
||||
if (IsMipsArchVariant(kMips32r2)) {
|
||||
n = m.Float64Sub(m.Float64Mul(p1, p2), p0);
|
||||
} else if (IsMipsArchVariant(kMips32r6)) {
|
||||
n = m.Float64Sub(p0, m.Float64Mul(p1, p2));
|
||||
}
|
||||
m.Return(n);
|
||||
Stream s = m.Build();
|
||||
ASSERT_EQ(1U, s.size());
|
||||
if (IsMipsArchVariant(kMips32r2)) {
|
||||
EXPECT_EQ(kMipsMsubD, s[0]->arch_opcode());
|
||||
} else if (IsMipsArchVariant(kMips32r6)) {
|
||||
EXPECT_EQ(kMipsMsubfD, s[0]->arch_opcode());
|
||||
}
|
||||
ASSERT_EQ(3U, s[0]->InputCount());
|
||||
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
||||
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
||||
EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2)));
|
||||
ASSERT_EQ(1U, s[0]->OutputCount());
|
||||
if (IsMipsArchVariant(kMips32r2)) {
|
||||
EXPECT_FALSE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
} else if (IsMipsArchVariant(kMips32r6)) {
|
||||
EXPECT_TRUE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
}
|
||||
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
||||
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
||||
}
|
||||
|
||||
TEST_F(InstructionSelectorTest, Float64Max) {
|
||||
StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(),
|
||||
|
||||
@ -1536,6 +1536,203 @@ TEST_F(InstructionSelectorTest, Float64Abs) {
|
||||
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
||||
}
|
||||
|
||||
TEST_F(InstructionSelectorTest, Float32AddWithFloat32Mul) {
|
||||
{
|
||||
StreamBuilder m(this, MachineType::Float32(), MachineType::Float32(),
|
||||
MachineType::Float32(), MachineType::Float32());
|
||||
Node* const p0 = m.Parameter(0);
|
||||
Node* const p1 = m.Parameter(1);
|
||||
Node* const p2 = m.Parameter(2);
|
||||
Node* const n = m.Float32Add(m.Float32Mul(p0, p1), p2);
|
||||
m.Return(n);
|
||||
Stream s = m.Build();
|
||||
ASSERT_EQ(1U, s.size());
|
||||
if (kArchVariant == kMips64r2) {
|
||||
EXPECT_EQ(kMips64MaddS, s[0]->arch_opcode());
|
||||
} else if (kArchVariant == kMips64r6) {
|
||||
EXPECT_EQ(kMips64MaddfS, s[0]->arch_opcode());
|
||||
}
|
||||
ASSERT_EQ(3U, s[0]->InputCount());
|
||||
EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(0)));
|
||||
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(1)));
|
||||
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(2)));
|
||||
ASSERT_EQ(1U, s[0]->OutputCount());
|
||||
if (kArchVariant == kMips64r2) {
|
||||
EXPECT_FALSE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
} else if (kArchVariant == kMips64r6) {
|
||||
EXPECT_TRUE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
}
|
||||
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
||||
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
||||
}
|
||||
{
|
||||
StreamBuilder m(this, MachineType::Float32(), MachineType::Float32(),
|
||||
MachineType::Float32(), MachineType::Float32());
|
||||
Node* const p0 = m.Parameter(0);
|
||||
Node* const p1 = m.Parameter(1);
|
||||
Node* const p2 = m.Parameter(2);
|
||||
Node* const n = m.Float32Add(p0, m.Float32Mul(p1, p2));
|
||||
m.Return(n);
|
||||
Stream s = m.Build();
|
||||
ASSERT_EQ(1U, s.size());
|
||||
if (kArchVariant == kMips64r2) {
|
||||
EXPECT_EQ(kMips64MaddS, s[0]->arch_opcode());
|
||||
} else if (kArchVariant == kMips64r6) {
|
||||
EXPECT_EQ(kMips64MaddfS, s[0]->arch_opcode());
|
||||
}
|
||||
ASSERT_EQ(3U, s[0]->InputCount());
|
||||
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
||||
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
||||
EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2)));
|
||||
ASSERT_EQ(1U, s[0]->OutputCount());
|
||||
if (kArchVariant == kMips64r2) {
|
||||
EXPECT_FALSE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
} else if (kArchVariant == kMips64r6) {
|
||||
EXPECT_TRUE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
}
|
||||
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
||||
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
||||
}
|
||||
}
|
||||
|
||||
TEST_F(InstructionSelectorTest, Float64AddWithFloat64Mul) {
|
||||
{
|
||||
StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(),
|
||||
MachineType::Float64(), MachineType::Float64());
|
||||
Node* const p0 = m.Parameter(0);
|
||||
Node* const p1 = m.Parameter(1);
|
||||
Node* const p2 = m.Parameter(2);
|
||||
Node* const n = m.Float64Add(m.Float64Mul(p0, p1), p2);
|
||||
m.Return(n);
|
||||
Stream s = m.Build();
|
||||
ASSERT_EQ(1U, s.size());
|
||||
if (kArchVariant == kMips64r2) {
|
||||
EXPECT_EQ(kMips64MaddD, s[0]->arch_opcode());
|
||||
} else if (kArchVariant == kMips64r6) {
|
||||
EXPECT_EQ(kMips64MaddfD, s[0]->arch_opcode());
|
||||
}
|
||||
ASSERT_EQ(3U, s[0]->InputCount());
|
||||
EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(0)));
|
||||
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(1)));
|
||||
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(2)));
|
||||
ASSERT_EQ(1U, s[0]->OutputCount());
|
||||
if (kArchVariant == kMips64r2) {
|
||||
EXPECT_FALSE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
} else if (kArchVariant == kMips64r6) {
|
||||
EXPECT_TRUE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
}
|
||||
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
||||
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
||||
}
|
||||
{
|
||||
StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(),
|
||||
MachineType::Float64(), MachineType::Float64());
|
||||
Node* const p0 = m.Parameter(0);
|
||||
Node* const p1 = m.Parameter(1);
|
||||
Node* const p2 = m.Parameter(2);
|
||||
Node* const n = m.Float64Add(p0, m.Float64Mul(p1, p2));
|
||||
m.Return(n);
|
||||
Stream s = m.Build();
|
||||
ASSERT_EQ(1U, s.size());
|
||||
if (kArchVariant == kMips64r2) {
|
||||
EXPECT_EQ(kMips64MaddD, s[0]->arch_opcode());
|
||||
} else if (kArchVariant == kMips64r6) {
|
||||
EXPECT_EQ(kMips64MaddfD, s[0]->arch_opcode());
|
||||
}
|
||||
ASSERT_EQ(3U, s[0]->InputCount());
|
||||
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
||||
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
||||
EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2)));
|
||||
ASSERT_EQ(1U, s[0]->OutputCount());
|
||||
if (kArchVariant == kMips64r2) {
|
||||
EXPECT_FALSE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
} else if (kArchVariant == kMips64r6) {
|
||||
EXPECT_TRUE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
}
|
||||
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
||||
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
||||
}
|
||||
}
|
||||
|
||||
TEST_F(InstructionSelectorTest, Float32SubWithFloat32Mul) {
|
||||
StreamBuilder m(this, MachineType::Float32(), MachineType::Float32(),
|
||||
MachineType::Float32(), MachineType::Float32());
|
||||
Node* const p0 = m.Parameter(0);
|
||||
Node* const p1 = m.Parameter(1);
|
||||
Node* const p2 = m.Parameter(2);
|
||||
Node* n;
|
||||
if (kArchVariant == kMips64r2) {
|
||||
n = m.Float32Sub(m.Float32Mul(p1, p2), p0);
|
||||
} else if (kArchVariant == kMips64r6) {
|
||||
n = m.Float32Sub(p0, m.Float32Mul(p1, p2));
|
||||
}
|
||||
m.Return(n);
|
||||
Stream s = m.Build();
|
||||
ASSERT_EQ(1U, s.size());
|
||||
if (kArchVariant == kMips64r2) {
|
||||
EXPECT_EQ(kMips64MsubS, s[0]->arch_opcode());
|
||||
} else if (kArchVariant == kMips64r6) {
|
||||
EXPECT_EQ(kMips64MsubfS, s[0]->arch_opcode());
|
||||
}
|
||||
ASSERT_EQ(3U, s[0]->InputCount());
|
||||
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
||||
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
||||
EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2)));
|
||||
ASSERT_EQ(1U, s[0]->OutputCount());
|
||||
if (kArchVariant == kMips64r2) {
|
||||
EXPECT_FALSE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
} else if (kArchVariant == kMips64r6) {
|
||||
EXPECT_TRUE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
}
|
||||
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
||||
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
||||
}
|
||||
|
||||
TEST_F(InstructionSelectorTest, Float64SubWithFloat64Mul) {
|
||||
StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(),
|
||||
MachineType::Float64(), MachineType::Float64());
|
||||
Node* const p0 = m.Parameter(0);
|
||||
Node* const p1 = m.Parameter(1);
|
||||
Node* const p2 = m.Parameter(2);
|
||||
Node* n;
|
||||
if (kArchVariant == kMips64r2) {
|
||||
n = m.Float64Sub(m.Float64Mul(p1, p2), p0);
|
||||
} else if (kArchVariant == kMips64r6) {
|
||||
n = m.Float64Sub(p0, m.Float64Mul(p1, p2));
|
||||
}
|
||||
m.Return(n);
|
||||
Stream s = m.Build();
|
||||
ASSERT_EQ(1U, s.size());
|
||||
if (kArchVariant == kMips64r2) {
|
||||
EXPECT_EQ(kMips64MsubD, s[0]->arch_opcode());
|
||||
} else if (kArchVariant == kMips64r6) {
|
||||
EXPECT_EQ(kMips64MsubfD, s[0]->arch_opcode());
|
||||
}
|
||||
ASSERT_EQ(3U, s[0]->InputCount());
|
||||
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
||||
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
||||
EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2)));
|
||||
ASSERT_EQ(1U, s[0]->OutputCount());
|
||||
if (kArchVariant == kMips64r2) {
|
||||
EXPECT_FALSE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
} else if (kArchVariant == kMips64r6) {
|
||||
EXPECT_TRUE(
|
||||
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
||||
}
|
||||
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
||||
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
||||
}
|
||||
|
||||
TEST_F(InstructionSelectorTest, Float64Max) {
|
||||
StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user