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PPC: [wasm-simd] refactor I16x8Mul and I8x16Mul on PPC

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Change-Id: If9bb55c0fa3297b5e0453cc9bc89bb906a905bf8
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2601342
Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#71877}
This commit is contained in:
Milad Fa 2020-12-24 09:21:27 -05:00 committed by Commit Bot
parent 32c29e8f01
commit 50e7dbacea
2 changed files with 26 additions and 13 deletions
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8
src/codegen/ppc/constants-ppc.h
View File

@ -2277,6 +2277,10 @@ using Instr = uint32_t;
V(vmuleub, VMULEUB, 0x10000208) \
/* Vector Multiply Odd Unsigned Byte */ \
V(vmuloub, VMULOUB, 0x10000008) \
/* Vector Multiply Even Unsigned Halfword */ \
V(vmuleuh, VMULEUH, 0x10000248) \
/* Vector Multiply Odd Unsigned Halfword */ \
V(vmulouh, VMULOUH, 0x10000048) \
/* Vector Sum across Quarter Signed Halfword Saturate */ \
V(vsum4shs, VSUM4SHS, 0x10000648) \
/* Vector Pack Unsigned Word Unsigned Saturate */ \
@ -2463,8 +2467,6 @@ using Instr = uint32_t;
V(vmulesh, VMULESH, 0x10000348) \
/* Vector Multiply Even Signed Word */ \
V(vmulesw, VMULESW, 0x10000388) \
/* Vector Multiply Even Unsigned Halfword */ \
V(vmuleuh, VMULEUH, 0x10000248) \
/* Vector Multiply Even Unsigned Word */ \
V(vmuleuw, VMULEUW, 0x10000288) \
/* Vector Multiply Odd Signed Byte */ \
@ -2473,8 +2475,6 @@ using Instr = uint32_t;
V(vmulosh, VMULOSH, 0x10000148) \
/* Vector Multiply Odd Signed Word */ \
V(vmulosw, VMULOSW, 0x10000188) \
/* Vector Multiply Odd Unsigned Halfword */ \
V(vmulouh, VMULOUH, 0x10000048) \
/* Vector Multiply Odd Unsigned Word */ \
V(vmulouw, VMULOUW, 0x10000088) \
/* Vector NAND */ \

31
src/compiler/backend/ppc/code-generator-ppc.cc
View File

@ -2514,9 +2514,17 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kPPC_I16x8Mul: {
__ vxor(kScratchSimd128Reg, kScratchSimd128Reg, kScratchSimd128Reg);
__ vmladduhm(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), kScratchSimd128Reg);
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register dst = i.OutputSimd128Register();
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
__ vmuleuh(kScratchSimd128Reg, src0, src1);
__ vmulouh(i.OutputSimd128Register(), src0, src1);
__ xxspltib(tempFPReg1, Operand(16));
__ vslw(kScratchSimd128Reg, kScratchSimd128Reg, tempFPReg1);
__ vslw(dst, dst, tempFPReg1);
__ vsrw(dst, dst, tempFPReg1);
__ vor(dst, kScratchSimd128Reg, dst);
break;
}
case kPPC_I8x16Add: {
@ -2530,12 +2538,17 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kPPC_I8x16Mul: {
__ vmuleub(kScratchSimd128Reg, i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ vmuloub(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ vpkuhum(i.OutputSimd128Register(), kScratchSimd128Reg,
i.OutputSimd128Register());
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register dst = i.OutputSimd128Register();
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
__ vmuleub(kScratchSimd128Reg, src0, src1);
__ vmuloub(i.OutputSimd128Register(), src0, src1);
__ xxspltib(tempFPReg1, Operand(8));
__ vslh(kScratchSimd128Reg, kScratchSimd128Reg, tempFPReg1);
__ vslh(dst, dst, tempFPReg1);
__ vsrh(dst, dst, tempFPReg1);
__ vor(dst, kScratchSimd128Reg, dst);
break;
}
case kPPC_I64x2MinS: {