AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

S390 [liftoff]: Implement simd unpack low/high ops

Browse Source 
Change-Id: Ie596dbb2041456e334d5cd7956a0717ccc7005c6
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3420832
Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/main@{#78846}
This commit is contained in:
Milad Fa 2022-01-27 15:45:56 -05:00 committed by V8 LUCI CQ
parent 98db248dc4
commit 5438399261
4 changed files with 153 additions and 217 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
src/codegen/s390/macro-assembler-s390.cc
View File

@ -5228,28 +5228,40 @@ void TurboAssembler::S128Not(Simd128Register dst, Simd128Register src) {
vno(dst, src, src, Condition(0), Condition(0), Condition(0));
}
#define SIMD_UNOP_LIST_VRR_A(V) \
V(F64x2Abs, vfpso, 2, 0, 3) \
V(F64x2Neg, vfpso, 0, 0, 3) \
V(F64x2Sqrt, vfsq, 0, 0, 3) \
V(F64x2Ceil, vfi, 6, 0, 3) \
V(F64x2Floor, vfi, 7, 0, 3) \
V(F64x2Trunc, vfi, 5, 0, 3) \
V(F64x2NearestInt, vfi, 4, 0, 3) \
V(F32x4Abs, vfpso, 2, 0, 2) \
V(F32x4Neg, vfpso, 0, 0, 2) \
V(F32x4Sqrt, vfsq, 0, 0, 2) \
V(F32x4Ceil, vfi, 6, 0, 2) \
V(F32x4Floor, vfi, 7, 0, 2) \
V(F32x4Trunc, vfi, 5, 0, 2) \
V(F32x4NearestInt, vfi, 4, 0, 2) \
V(I64x2Abs, vlp, 0, 0, 3) \
V(I32x4Abs, vlp, 0, 0, 2) \
V(I16x8Abs, vlp, 0, 0, 1) \
V(I8x16Abs, vlp, 0, 0, 0) \
V(I64x2Neg, vlc, 0, 0, 3) \
V(I32x4Neg, vlc, 0, 0, 2) \
V(I16x8Neg, vlc, 0, 0, 1) \
#define SIMD_UNOP_LIST_VRR_A(V) \
V(F64x2Abs, vfpso, 2, 0, 3) \
V(F64x2Neg, vfpso, 0, 0, 3) \
V(F64x2Sqrt, vfsq, 0, 0, 3) \
V(F64x2Ceil, vfi, 6, 0, 3) \
V(F64x2Floor, vfi, 7, 0, 3) \
V(F64x2Trunc, vfi, 5, 0, 3) \
V(F64x2NearestInt, vfi, 4, 0, 3) \
V(F32x4Abs, vfpso, 2, 0, 2) \
V(F32x4Neg, vfpso, 0, 0, 2) \
V(F32x4Sqrt, vfsq, 0, 0, 2) \
V(F32x4Ceil, vfi, 6, 0, 2) \
V(F32x4Floor, vfi, 7, 0, 2) \
V(F32x4Trunc, vfi, 5, 0, 2) \
V(F32x4NearestInt, vfi, 4, 0, 2) \
V(I64x2Abs, vlp, 0, 0, 3) \
V(I64x2Neg, vlc, 0, 0, 3) \
V(I64x2SConvertI32x4Low, vupl, 0, 0, 2) \
V(I64x2SConvertI32x4High, vuph, 0, 0, 2) \
V(I64x2UConvertI32x4Low, vupll, 0, 0, 2) \
V(I64x2UConvertI32x4High, vuplh, 0, 0, 2) \
V(I32x4Abs, vlp, 0, 0, 2) \
V(I32x4Neg, vlc, 0, 0, 2) \
V(I32x4SConvertI16x8Low, vupl, 0, 0, 1) \
V(I32x4SConvertI16x8High, vuph, 0, 0, 1) \
V(I32x4UConvertI16x8Low, vupll, 0, 0, 1) \
V(I32x4UConvertI16x8High, vuplh, 0, 0, 1) \
V(I16x8Abs, vlp, 0, 0, 1) \
V(I16x8Neg, vlc, 0, 0, 1) \
V(I16x8SConvertI8x16Low, vupl, 0, 0, 0) \
V(I16x8SConvertI8x16High, vuph, 0, 0, 0) \
V(I16x8UConvertI8x16Low, vupll, 0, 0, 0) \
V(I16x8UConvertI8x16High, vuplh, 0, 0, 0) \
V(I8x16Abs, vlp, 0, 0, 0) \
V(I8x16Neg, vlc, 0, 0, 0)
#define EMIT_SIMD_UNOP_VRR_A(name, op, c1, c2, c3) \

62
src/codegen/s390/macro-assembler-s390.h
View File

@ -1114,31 +1114,43 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
void I8x16BitMask(Register dst, Simd128Register src, Register scratch1,
Register scratch2, Simd128Register scratch3);
#define SIMD_UNOP_LIST(V) \
V(F64x2Abs) \
V(F64x2Neg) \
V(F64x2Sqrt) \
V(F64x2Ceil) \
V(F64x2Floor) \
V(F64x2Trunc) \
V(F64x2NearestInt) \
V(F64x2ConvertLowI32x4S) \
V(F64x2ConvertLowI32x4U) \
V(F32x4Abs) \
V(F32x4Neg) \
V(F32x4Sqrt) \
V(F32x4Ceil) \
V(F32x4Floor) \
V(F32x4Trunc) \
V(F32x4NearestInt) \
V(I64x2Abs) \
V(I32x4Abs) \
V(I16x8Abs) \
V(I8x16Abs) \
V(I64x2Neg) \
V(I32x4Neg) \
V(I16x8Neg) \
V(I8x16Neg) \
#define SIMD_UNOP_LIST(V) \
V(F64x2Abs) \
V(F64x2Neg) \
V(F64x2Sqrt) \
V(F64x2Ceil) \
V(F64x2Floor) \
V(F64x2Trunc) \
V(F64x2NearestInt) \
V(F64x2ConvertLowI32x4S) \
V(F64x2ConvertLowI32x4U) \
V(F32x4Abs) \
V(F32x4Neg) \
V(F32x4Sqrt) \
V(F32x4Ceil) \
V(F32x4Floor) \
V(F32x4Trunc) \
V(F32x4NearestInt) \
V(I64x2Abs) \
V(I64x2SConvertI32x4Low) \
V(I64x2SConvertI32x4High) \
V(I64x2UConvertI32x4Low) \
V(I64x2UConvertI32x4High) \
V(I64x2Neg) \
V(I32x4Abs) \
V(I32x4Neg) \
V(I32x4SConvertI16x8Low) \
V(I32x4SConvertI16x8High) \
V(I32x4UConvertI16x8Low) \
V(I32x4UConvertI16x8High) \
V(I16x8Abs) \
V(I16x8Neg) \
V(I16x8SConvertI8x16Low) \
V(I16x8SConvertI8x16High) \
V(I16x8UConvertI8x16Low) \
V(I16x8UConvertI8x16High) \
V(I8x16Abs) \
V(I8x16Neg) \
V(S128Not)
#define PROTOTYPE_SIMD_UNOP(name) \

122
src/compiler/backend/s390/code-generator-s390.cc
View File

@ -2651,35 +2651,47 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
#undef EMIT_SIMD_BINOP
#undef SIMD_BINOP_LIST
#define SIMD_UNOP_LIST(V) \
V(F64x2Splat, Simd128Register, DoubleRegister) \
V(F32x4Splat, Simd128Register, DoubleRegister) \
V(I64x2Splat, Simd128Register, Register) \
V(I32x4Splat, Simd128Register, Register) \
V(I16x8Splat, Simd128Register, Register) \
V(I8x16Splat, Simd128Register, Register) \
V(F64x2Abs, Simd128Register, Simd128Register) \
V(F64x2Neg, Simd128Register, Simd128Register) \
V(F64x2Sqrt, Simd128Register, Simd128Register) \
V(F64x2Ceil, Simd128Register, Simd128Register) \
V(F64x2Floor, Simd128Register, Simd128Register) \
V(F64x2Trunc, Simd128Register, Simd128Register) \
V(F64x2NearestInt, Simd128Register, Simd128Register) \
V(F32x4Abs, Simd128Register, Simd128Register) \
V(F32x4Neg, Simd128Register, Simd128Register) \
V(F32x4Sqrt, Simd128Register, Simd128Register) \
V(F32x4Ceil, Simd128Register, Simd128Register) \
V(F32x4Floor, Simd128Register, Simd128Register) \
V(F32x4Trunc, Simd128Register, Simd128Register) \
V(F32x4NearestInt, Simd128Register, Simd128Register) \
V(I64x2Abs, Simd128Register, Simd128Register) \
V(I32x4Abs, Simd128Register, Simd128Register) \
V(I16x8Abs, Simd128Register, Simd128Register) \
V(I8x16Abs, Simd128Register, Simd128Register) \
V(I64x2Neg, Simd128Register, Simd128Register) \
V(I32x4Neg, Simd128Register, Simd128Register) \
V(I16x8Neg, Simd128Register, Simd128Register) \
V(I8x16Neg, Simd128Register, Simd128Register) \
#define SIMD_UNOP_LIST(V) \
V(F64x2Splat, Simd128Register, DoubleRegister) \
V(F64x2Abs, Simd128Register, Simd128Register) \
V(F64x2Neg, Simd128Register, Simd128Register) \
V(F64x2Sqrt, Simd128Register, Simd128Register) \
V(F64x2Ceil, Simd128Register, Simd128Register) \
V(F64x2Floor, Simd128Register, Simd128Register) \
V(F64x2Trunc, Simd128Register, Simd128Register) \
V(F64x2NearestInt, Simd128Register, Simd128Register) \
V(F32x4Splat, Simd128Register, DoubleRegister) \
V(F32x4Abs, Simd128Register, Simd128Register) \
V(F32x4Neg, Simd128Register, Simd128Register) \
V(F32x4Sqrt, Simd128Register, Simd128Register) \
V(F32x4Ceil, Simd128Register, Simd128Register) \
V(F32x4Floor, Simd128Register, Simd128Register) \
V(F32x4Trunc, Simd128Register, Simd128Register) \
V(F32x4NearestInt, Simd128Register, Simd128Register) \
V(I64x2Splat, Simd128Register, Register) \
V(I64x2Abs, Simd128Register, Simd128Register) \
V(I64x2Neg, Simd128Register, Simd128Register) \
V(I64x2SConvertI32x4Low, Simd128Register, Simd128Register) \
V(I64x2SConvertI32x4High, Simd128Register, Simd128Register) \
V(I64x2UConvertI32x4Low, Simd128Register, Simd128Register) \
V(I64x2UConvertI32x4High, Simd128Register, Simd128Register) \
V(I32x4Splat, Simd128Register, Register) \
V(I32x4Abs, Simd128Register, Simd128Register) \
V(I32x4Neg, Simd128Register, Simd128Register) \
V(I32x4SConvertI16x8Low, Simd128Register, Simd128Register) \
V(I32x4SConvertI16x8High, Simd128Register, Simd128Register) \
V(I32x4UConvertI16x8Low, Simd128Register, Simd128Register) \
V(I32x4UConvertI16x8High, Simd128Register, Simd128Register) \
V(I16x8Splat, Simd128Register, Register) \
V(I16x8Abs, Simd128Register, Simd128Register) \
V(I16x8Neg, Simd128Register, Simd128Register) \
V(I16x8SConvertI8x16Low, Simd128Register, Simd128Register) \
V(I16x8SConvertI8x16High, Simd128Register, Simd128Register) \
V(I16x8UConvertI8x16Low, Simd128Register, Simd128Register) \
V(I16x8UConvertI8x16High, Simd128Register, Simd128Register) \
V(I8x16Splat, Simd128Register, Register) \
V(I8x16Abs, Simd128Register, Simd128Register) \
V(I8x16Neg, Simd128Register, Simd128Register) \
V(S128Not, Simd128Register, Simd128Register)
#define EMIT_SIMD_UNOP(name, dtype, stype) \
@ -2959,58 +2971,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
#undef CONVERT_INT32_TO_FLOAT
#define VECTOR_UNPACK(op, mode) \
__ op(i.OutputSimd128Register(), i.InputSimd128Register(0), Condition(0), \
Condition(0), Condition(mode));
case kS390_I64x2SConvertI32x4Low: {
VECTOR_UNPACK(vupl, 2)
break;
}
case kS390_I64x2SConvertI32x4High: {
VECTOR_UNPACK(vuph, 2)
break;
}
case kS390_I64x2UConvertI32x4Low: {
VECTOR_UNPACK(vupll, 2)
break;
}
case kS390_I64x2UConvertI32x4High: {
VECTOR_UNPACK(vuplh, 2)
break;
}
case kS390_I32x4SConvertI16x8Low: {
VECTOR_UNPACK(vupl, 1)
break;
}
case kS390_I32x4SConvertI16x8High: {
VECTOR_UNPACK(vuph, 1)
break;
}
case kS390_I32x4UConvertI16x8Low: {
VECTOR_UNPACK(vupll, 1)
break;
}
case kS390_I32x4UConvertI16x8High: {
VECTOR_UNPACK(vuplh, 1)
break;
}
case kS390_I16x8SConvertI8x16Low: {
VECTOR_UNPACK(vupl, 0)
break;
}
case kS390_I16x8SConvertI8x16High: {
VECTOR_UNPACK(vuph, 0)
break;
}
case kS390_I16x8UConvertI8x16Low: {
VECTOR_UNPACK(vupll, 0)
break;
}
case kS390_I16x8UConvertI8x16High: {
VECTOR_UNPACK(vuplh, 0)
break;
}
#undef VECTOR_UNPACK
case kS390_I16x8SConvertI32x4:
__ vpks(i.OutputSimd128Register(), i.InputSimd128Register(1),
i.InputSimd128Register(0), Condition(0), Condition(2));

130
src/wasm/baseline/s390/liftoff-assembler-s390.h
View File

@ -2384,35 +2384,47 @@ SIMD_BINOP_RI_LIST(EMIT_SIMD_BINOP_RI)
#undef EMIT_SIMD_BINOP_RI
#undef SIMD_BINOP_RI_LIST
#define SIMD_UNOP_LIST(V) \
V(f64x2_splat, F64x2Splat, fp, fp, , void) \
V(f32x4_splat, F32x4Splat, fp, fp, , void) \
V(i64x2_splat, I64x2Splat, fp, gp, , void) \
V(i32x4_splat, I32x4Splat, fp, gp, , void) \
V(i16x8_splat, I16x8Splat, fp, gp, , void) \
V(i8x16_splat, I8x16Splat, fp, gp, , void) \
V(f64x2_abs, F64x2Abs, fp, fp, , void) \
V(f64x2_neg, F64x2Neg, fp, fp, , void) \
V(f64x2_sqrt, F64x2Sqrt, fp, fp, , void) \
V(f64x2_ceil, F64x2Ceil, fp, fp, true, bool) \
V(f64x2_floor, F64x2Floor, fp, fp, true, bool) \
V(f64x2_trunc, F64x2Trunc, fp, fp, true, bool) \
V(f64x2_nearest_int, F64x2NearestInt, fp, fp, true, bool) \
V(f32x4_abs, F32x4Abs, fp, fp, , void) \
V(f32x4_neg, F32x4Neg, fp, fp, , void) \
V(f32x4_sqrt, F32x4Sqrt, fp, fp, , void) \
V(f32x4_ceil, F32x4Ceil, fp, fp, true, bool) \
V(f32x4_floor, F32x4Floor, fp, fp, true, bool) \
V(f32x4_trunc, F32x4Trunc, fp, fp, true, bool) \
V(f32x4_nearest_int, F32x4NearestInt, fp, fp, true, bool) \
V(i64x2_abs, I64x2Abs, fp, fp, , void) \
V(i32x4_abs, I32x4Abs, fp, fp, , void) \
V(i16x8_abs, I16x8Abs, fp, fp, , void) \
V(i8x16_abs, I8x16Abs, fp, fp, , void) \
V(i64x2_neg, I64x2Neg, fp, fp, , void) \
V(i32x4_neg, I32x4Neg, fp, fp, , void) \
V(i16x8_neg, I16x8Neg, fp, fp, , void) \
V(i8x16_neg, I8x16Neg, fp, fp, , void) \
#define SIMD_UNOP_LIST(V) \
V(f64x2_splat, F64x2Splat, fp, fp, , void) \
V(f64x2_abs, F64x2Abs, fp, fp, , void) \
V(f64x2_neg, F64x2Neg, fp, fp, , void) \
V(f64x2_sqrt, F64x2Sqrt, fp, fp, , void) \
V(f64x2_ceil, F64x2Ceil, fp, fp, true, bool) \
V(f64x2_floor, F64x2Floor, fp, fp, true, bool) \
V(f64x2_trunc, F64x2Trunc, fp, fp, true, bool) \
V(f64x2_nearest_int, F64x2NearestInt, fp, fp, true, bool) \
V(f32x4_abs, F32x4Abs, fp, fp, , void) \
V(f32x4_splat, F32x4Splat, fp, fp, , void) \
V(f32x4_neg, F32x4Neg, fp, fp, , void) \
V(f32x4_sqrt, F32x4Sqrt, fp, fp, , void) \
V(f32x4_ceil, F32x4Ceil, fp, fp, true, bool) \
V(f32x4_floor, F32x4Floor, fp, fp, true, bool) \
V(f32x4_trunc, F32x4Trunc, fp, fp, true, bool) \
V(f32x4_nearest_int, F32x4NearestInt, fp, fp, true, bool) \
V(i64x2_abs, I64x2Abs, fp, fp, , void) \
V(i64x2_splat, I64x2Splat, fp, gp, , void) \
V(i64x2_neg, I64x2Neg, fp, fp, , void) \
V(i64x2_sconvert_i32x4_low, I64x2SConvertI32x4Low, fp, fp, , void) \
V(i64x2_sconvert_i32x4_high, I64x2SConvertI32x4High, fp, fp, , void) \
V(i64x2_uconvert_i32x4_low, I64x2UConvertI32x4Low, fp, fp, , void) \
V(i64x2_uconvert_i32x4_high, I64x2UConvertI32x4High, fp, fp, , void) \
V(i32x4_abs, I32x4Abs, fp, fp, , void) \
V(i32x4_neg, I32x4Neg, fp, fp, , void) \
V(i32x4_splat, I32x4Splat, fp, gp, , void) \
V(i32x4_sconvert_i16x8_low, I32x4SConvertI16x8Low, fp, fp, , void) \
V(i32x4_sconvert_i16x8_high, I32x4SConvertI16x8High, fp, fp, , void) \
V(i32x4_uconvert_i16x8_low, I32x4UConvertI16x8Low, fp, fp, , void) \
V(i32x4_uconvert_i16x8_high, I32x4UConvertI16x8High, fp, fp, , void) \
V(i16x8_abs, I16x8Abs, fp, fp, , void) \
V(i16x8_neg, I16x8Neg, fp, fp, , void) \
V(i16x8_splat, I16x8Splat, fp, gp, , void) \
V(i16x8_sconvert_i8x16_low, I16x8SConvertI8x16Low, fp, fp, , void) \
V(i16x8_sconvert_i8x16_high, I16x8SConvertI8x16High, fp, fp, , void) \
V(i16x8_uconvert_i8x16_low, I16x8UConvertI8x16Low, fp, fp, , void) \
V(i16x8_uconvert_i8x16_high, I16x8UConvertI8x16High, fp, fp, , void) \
V(i8x16_abs, I8x16Abs, fp, fp, , void) \
V(i8x16_neg, I8x16Neg, fp, fp, , void) \
V(i8x16_splat, I8x16Splat, fp, gp, , void) \
V(s128_not, S128Not, fp, fp, , void)
#define EMIT_SIMD_UNOP(name, op, dtype, stype, return_val, return_type) \
@ -2538,26 +2550,6 @@ void LiftoffAssembler::emit_i64x2_bitmask(LiftoffRegister dst,
I64x2BitMask(dst.gp(), src.fp(), r0, kScratchDoubleReg);
}
void LiftoffAssembler::emit_i64x2_sconvert_i32x4_low(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "i64x2_sconvert_i32x4_low");
}
void LiftoffAssembler::emit_i64x2_sconvert_i32x4_high(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "i64x2_sconvert_i32x4_high");
}
void LiftoffAssembler::emit_i64x2_uconvert_i32x4_low(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "i64x2_uconvert_i32x4_low");
}
void LiftoffAssembler::emit_i64x2_uconvert_i32x4_high(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "i64x2_uconvert_i32x4_high");
}
void LiftoffAssembler::emit_i32x4_alltrue(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "i32x4_alltrue");
@ -2747,46 +2739,6 @@ void LiftoffAssembler::emit_i16x8_uconvert_i32x4(LiftoffRegister dst,
bailout(kUnsupportedArchitecture, "emit_i16x8_uconvert_i32x4");
}
void LiftoffAssembler::emit_i16x8_sconvert_i8x16_low(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_i16x8_sconvert_i8x16_low");
}
void LiftoffAssembler::emit_i16x8_sconvert_i8x16_high(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_i16x8_sconvert_i8x16_high");
}
void LiftoffAssembler::emit_i16x8_uconvert_i8x16_low(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_i16x8_uconvert_i8x16_low");
}
void LiftoffAssembler::emit_i16x8_uconvert_i8x16_high(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_i16x8_uconvert_i8x16_high");
}
void LiftoffAssembler::emit_i32x4_sconvert_i16x8_low(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_i32x4_sconvert_i16x8_low");
}
void LiftoffAssembler::emit_i32x4_sconvert_i16x8_high(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_i32x4_sconvert_i16x8_high");
}
void LiftoffAssembler::emit_i32x4_uconvert_i16x8_low(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_i32x4_uconvert_i16x8_low");
}
void LiftoffAssembler::emit_i32x4_uconvert_i16x8_high(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_i32x4_uconvert_i16x8_high");
}
void LiftoffAssembler::emit_i32x4_trunc_sat_f64x2_s_zero(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "i32x4.trunc_sat_f64x2_s_zero");