Fix disasm assertions for undefined instructions.
BUG=none TEST=none Review URL: https://chromiumcodereview.appspot.com/9228006 Patch from Martyn Capewell <m.m.capewell@googlemail.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10498 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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@ -662,6 +662,15 @@ void Decoder::Format(Instruction* instr, const char* format) {
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}
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// The disassembler may end up decoding data inlined in the code. We do not want
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// it to crash if the data does not ressemble any known instruction.
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#define VERIFY(condition) \
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if(!(condition)) { \
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Unknown(instr); \
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return; \
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}
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// For currently unimplemented decodings the disassembler calls Unknown(instr)
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// which will just print "unknown" of the instruction bits.
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void Decoder::Unknown(Instruction* instr) {
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@ -947,13 +956,13 @@ void Decoder::DecodeType2(Instruction* instr) {
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void Decoder::DecodeType3(Instruction* instr) {
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switch (instr->PUField()) {
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case da_x: {
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ASSERT(!instr->HasW());
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VERIFY(!instr->HasW());
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Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
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break;
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}
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case ia_x: {
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if (instr->HasW()) {
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ASSERT(instr->Bits(5, 4) == 0x1);
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VERIFY(instr->Bits(5, 4) == 0x1);
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if (instr->Bit(22) == 0x1) {
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Format(instr, "usat 'rd, #'imm05@16, 'rm'shift_sat");
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} else {
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@ -1074,8 +1083,8 @@ int Decoder::DecodeType7(Instruction* instr) {
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// vmsr
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// Dd = vsqrt(Dm)
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void Decoder::DecodeTypeVFP(Instruction* instr) {
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ASSERT((instr->TypeValue() == 7) && (instr->Bit(24) == 0x0) );
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ASSERT(instr->Bits(11, 9) == 0x5);
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VERIFY((instr->TypeValue() == 7) && (instr->Bit(24) == 0x0) );
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VERIFY(instr->Bits(11, 9) == 0x5);
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if (instr->Bit(4) == 0) {
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if (instr->Opc1Value() == 0x7) {
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@ -1166,7 +1175,7 @@ void Decoder::DecodeTypeVFP(Instruction* instr) {
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void Decoder::DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(
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Instruction* instr) {
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ASSERT((instr->Bit(4) == 1) && (instr->VCValue() == 0x0) &&
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VERIFY((instr->Bit(4) == 1) && (instr->VCValue() == 0x0) &&
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(instr->VAValue() == 0x0));
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bool to_arm_register = (instr->VLValue() == 0x1);
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@ -1180,8 +1189,8 @@ void Decoder::DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(
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void Decoder::DecodeVCMP(Instruction* instr) {
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ASSERT((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
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ASSERT(((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
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VERIFY((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
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VERIFY(((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
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(instr->Opc3Value() & 0x1));
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// Comparison.
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@ -1203,8 +1212,8 @@ void Decoder::DecodeVCMP(Instruction* instr) {
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void Decoder::DecodeVCVTBetweenDoubleAndSingle(Instruction* instr) {
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ASSERT((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
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ASSERT((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3));
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VERIFY((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
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VERIFY((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3));
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bool double_to_single = (instr->SzValue() == 1);
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@ -1217,8 +1226,8 @@ void Decoder::DecodeVCVTBetweenDoubleAndSingle(Instruction* instr) {
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void Decoder::DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr) {
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ASSERT((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
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ASSERT(((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) ||
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VERIFY((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
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VERIFY(((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) ||
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(((instr->Opc2Value() >> 1) == 0x6) && (instr->Opc3Value() & 0x1)));
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bool to_integer = (instr->Bit(18) == 1);
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@ -1265,7 +1274,7 @@ void Decoder::DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr) {
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// Ddst = MEM(Rbase + 4*offset).
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// MEM(Rbase + 4*offset) = Dsrc.
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void Decoder::DecodeType6CoprocessorIns(Instruction* instr) {
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ASSERT(instr->TypeValue() == 6);
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VERIFY(instr->TypeValue() == 6);
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if (instr->CoprocessorValue() == 0xA) {
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switch (instr->OpcodeValue()) {
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@ -1347,6 +1356,7 @@ void Decoder::DecodeType6CoprocessorIns(Instruction* instr) {
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}
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}
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#undef VERIFIY
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bool Decoder::IsConstantPoolAt(byte* instr_ptr) {
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int instruction_bits = *(reinterpret_cast<int*>(instr_ptr));
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