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[wasm-simd][arm][liftoff] Implement i64x2.ne

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Accidentally omitted this in a previous change
https://crrev.com/c/2686013.

Extract code sequence into macro-assembler for sharing between Liftoff
and TurboFan.

Bug: v8:11348
Change-Id: Ia4e9d1e0dc7a7f3a1a21ff1e1745923a847328cf
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2707773
Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#73032}
This commit is contained in:
Ng Zhi An 2021-02-22 13:27:28 -08:00 committed by Commit Bot
parent 6045ba6dae
commit 574ff78bfb
7 changed files with 30 additions and 9 deletions
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9
src/codegen/arm/assembler-arm.cc
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@ -4248,6 +4248,15 @@ void Assembler::vorr(QwNeonRegister dst, QwNeonRegister src1,
src2.code()));
}
void Assembler::vorn(QwNeonRegister dst, QwNeonRegister src1,
QwNeonRegister src2) {
// Qd = vorn(Qn, Qm) SIMD OR NOT.
// Instruction details available in ARM DDI 0406C.d, A8.8.359.
DCHECK(IsEnabled(NEON));
emit(EncodeNeonBinaryBitwiseOp(VORN, NEON_Q, dst.code(), src1.code(),
src2.code()));
}
enum FPBinOp {
VADDF,
VSUBF,

1
src/codegen/arm/assembler-arm.h
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@ -887,6 +887,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
void veor(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
void vbsl(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
void vorr(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
void vorn(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
void vadd(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
void vadd(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
QwNeonRegister src2);

10
src/codegen/arm/macro-assembler-arm.cc
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@ -2650,6 +2650,16 @@ void TurboAssembler::I64x2Eq(QwNeonRegister dst, QwNeonRegister src1,
vand(dst, dst, scratch);
}
void TurboAssembler::I64x2Ne(QwNeonRegister dst, QwNeonRegister src1,
QwNeonRegister src2) {
UseScratchRegisterScope temps(this);
Simd128Register tmp = temps.AcquireQ();
vceq(Neon32, dst, src1, src2);
vrev64(Neon32, tmp, dst);
vmvn(dst, dst);
vorn(dst, dst, tmp);
}
void TurboAssembler::I64x2GtS(QwNeonRegister dst, QwNeonRegister src1,
QwNeonRegister src2) {
vqsub(NeonS64, dst, src2, src1);

1
src/codegen/arm/macro-assembler-arm.h
View File

@ -571,6 +571,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
// and be used in both TurboFan and Liftoff.
void I64x2BitMask(Register dst, QwNeonRegister src);
void I64x2Eq(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
void I64x2Ne(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
void I64x2GtS(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
void I64x2GeS(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
void V64x2AllTrue(Register dst, QwNeonRegister src);

10
src/compiler/backend/arm/code-generator-arm.cc
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@ -2449,14 +2449,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kArmI64x2Ne: {
Simd128Register dst = i.OutputSimd128Register();
UseScratchRegisterScope temps(tasm());
Simd128Register tmp = temps.AcquireQ();
__ vceq(Neon32, dst, i.InputSimd128Register(0),
i.InputSimd128Register(1));
__ vrev64(Neon32, tmp, dst);
__ vand(dst, dst, tmp);
__ vmvn(dst, dst);
__ I64x2Ne(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kArmI64x2GtS: {

5
src/execution/arm/simulator-arm.cc
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@ -5034,6 +5034,11 @@ void Simulator::DecodeAdvancedSIMDDataProcessing(Instruction* instr) {
}
}
set_neon_register(Vd, src1);
} else if (!u && opc == 1 && sz == 3 && q && op1) {
// vorn, Qd, Qm, Qn.
// NeonSize does not matter.
Binop<uint32_t>(this, Vd, Vm, Vn,
[](uint32_t x, uint32_t y) { return x | (~y); });
} else if (!u && opc == 1 && sz == 0 && q && op1) {
// vand Qd, Qm, Qn.
uint32_t src1[4], src2[4];

3
src/wasm/baseline/arm/liftoff-assembler-arm.h
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@ -3771,7 +3771,8 @@ void LiftoffAssembler::emit_i64x2_eq(LiftoffRegister dst, LiftoffRegister lhs,
void LiftoffAssembler::emit_i64x2_ne(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kSimd, "i64x2_ne");
I64x2Ne(liftoff::GetSimd128Register(dst), liftoff::GetSimd128Register(lhs),
liftoff::GetSimd128Register(rhs));
}
void LiftoffAssembler::emit_i64x2_gt_s(LiftoffRegister dst, LiftoffRegister lhs,