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MIPS: [turbofan] Fix several int vs size_t issues.

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Port 9c1407da78

BUG=

Review URL: https://codereview.chromium.org/948843002

Cr-Commit-Position: refs/heads/master@{#26797}
This commit is contained in:
balazs.kilvady 2015-02-23 05:59:14 -08:00 committed by Commit bot
parent 7361dce458
commit 585e50c3fd
2 changed files with 18 additions and 18 deletions
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18
src/compiler/mips/code-generator-mips.cc
View File

@ -39,11 +39,11 @@ class MipsOperandConverter FINAL : public InstructionOperandConverter {
MipsOperandConverter(CodeGenerator* gen, Instruction* instr) MipsOperandConverter(CodeGenerator* gen, Instruction* instr)
: InstructionOperandConverter(gen, instr) {} : InstructionOperandConverter(gen, instr) {}
FloatRegister OutputSingleRegister(int index = 0) { FloatRegister OutputSingleRegister(size_t index = 0) {
return ToSingleRegister(instr_->OutputAt(index)); return ToSingleRegister(instr_->OutputAt(index));
} }
FloatRegister InputSingleRegister(int index) { FloatRegister InputSingleRegister(size_t index) {
return ToSingleRegister(instr_->InputAt(index)); return ToSingleRegister(instr_->InputAt(index));
} }
@ -53,7 +53,7 @@ class MipsOperandConverter FINAL : public InstructionOperandConverter {
return ToDoubleRegister(op); return ToDoubleRegister(op);
} }
Operand InputImmediate(int index) { Operand InputImmediate(size_t index) {
Constant constant = ToConstant(instr_->InputAt(index)); Constant constant = ToConstant(instr_->InputAt(index));
switch (constant.type()) { switch (constant.type()) {
case Constant::kInt32: case Constant::kInt32:
@ -78,7 +78,7 @@ class MipsOperandConverter FINAL : public InstructionOperandConverter {
return Operand(zero_reg); return Operand(zero_reg);
} }
Operand InputOperand(int index) { Operand InputOperand(size_t index) {
InstructionOperand* op = instr_->InputAt(index); InstructionOperand* op = instr_->InputAt(index);
if (op->IsRegister()) { if (op->IsRegister()) {
return Operand(ToRegister(op)); return Operand(ToRegister(op));
@ -86,8 +86,8 @@ class MipsOperandConverter FINAL : public InstructionOperandConverter {
return InputImmediate(index); return InputImmediate(index);
} }
MemOperand MemoryOperand(int* first_index) { MemOperand MemoryOperand(size_t* first_index) {
const int index = *first_index; const size_t index = *first_index;
switch (AddressingModeField::decode(instr_->opcode())) { switch (AddressingModeField::decode(instr_->opcode())) {
case kMode_None: case kMode_None:
break; break;
@ -102,7 +102,7 @@ class MipsOperandConverter FINAL : public InstructionOperandConverter {
return MemOperand(no_reg); return MemOperand(no_reg);
} }
MemOperand MemoryOperand(int index = 0) { return MemoryOperand(&index); } MemOperand MemoryOperand(size_t index = 0) { return MemoryOperand(&index); }
MemOperand ToMemOperand(InstructionOperand* op) const { MemOperand ToMemOperand(InstructionOperand* op) const {
DCHECK(op != NULL); DCHECK(op != NULL);
@ -116,7 +116,7 @@ class MipsOperandConverter FINAL : public InstructionOperandConverter {
}; };
static inline bool HasRegisterInput(Instruction* instr, int index) { static inline bool HasRegisterInput(Instruction* instr, size_t index) {
return instr->InputAt(index)->IsRegister(); return instr->InputAt(index)->IsRegister();
} }
@ -646,7 +646,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
break; break;
} }
case kMipsSwc1: { case kMipsSwc1: {
int index = 0; size_t index = 0;
MemOperand operand = i.MemoryOperand(&index); MemOperand operand = i.MemoryOperand(&index);
__ swc1(i.InputSingleRegister(index), operand); __ swc1(i.InputSingleRegister(index), operand);
break; break;

18
src/compiler/mips64/code-generator-mips64.cc
View File

@ -38,11 +38,11 @@ class MipsOperandConverter FINAL : public InstructionOperandConverter {
MipsOperandConverter(CodeGenerator* gen, Instruction* instr) MipsOperandConverter(CodeGenerator* gen, Instruction* instr)
: InstructionOperandConverter(gen, instr) {} : InstructionOperandConverter(gen, instr) {}
FloatRegister OutputSingleRegister(int index = 0) { FloatRegister OutputSingleRegister(size_t index = 0) {
return ToSingleRegister(instr_->OutputAt(index)); return ToSingleRegister(instr_->OutputAt(index));
} }
FloatRegister InputSingleRegister(int index) { FloatRegister InputSingleRegister(size_t index) {
return ToSingleRegister(instr_->InputAt(index)); return ToSingleRegister(instr_->InputAt(index));
} }
@ -52,7 +52,7 @@ class MipsOperandConverter FINAL : public InstructionOperandConverter {
return ToDoubleRegister(op); return ToDoubleRegister(op);
} }
Operand InputImmediate(int index) { Operand InputImmediate(size_t index) {
Constant constant = ToConstant(instr_->InputAt(index)); Constant constant = ToConstant(instr_->InputAt(index));
switch (constant.type()) { switch (constant.type()) {
case Constant::kInt32: case Constant::kInt32:
@ -78,7 +78,7 @@ class MipsOperandConverter FINAL : public InstructionOperandConverter {
return Operand(zero_reg); return Operand(zero_reg);
} }
Operand InputOperand(int index) { Operand InputOperand(size_t index) {
InstructionOperand* op = instr_->InputAt(index); InstructionOperand* op = instr_->InputAt(index);
if (op->IsRegister()) { if (op->IsRegister()) {
return Operand(ToRegister(op)); return Operand(ToRegister(op));
@ -86,8 +86,8 @@ class MipsOperandConverter FINAL : public InstructionOperandConverter {
return InputImmediate(index); return InputImmediate(index);
} }
MemOperand MemoryOperand(int* first_index) { MemOperand MemoryOperand(size_t* first_index) {
const int index = *first_index; const size_t index = *first_index;
switch (AddressingModeField::decode(instr_->opcode())) { switch (AddressingModeField::decode(instr_->opcode())) {
case kMode_None: case kMode_None:
break; break;
@ -102,7 +102,7 @@ class MipsOperandConverter FINAL : public InstructionOperandConverter {
return MemOperand(no_reg); return MemOperand(no_reg);
} }
MemOperand MemoryOperand(int index = 0) { return MemoryOperand(&index); } MemOperand MemoryOperand(size_t index = 0) { return MemoryOperand(&index); }
MemOperand ToMemOperand(InstructionOperand* op) const { MemOperand ToMemOperand(InstructionOperand* op) const {
DCHECK(op != NULL); DCHECK(op != NULL);
@ -116,7 +116,7 @@ class MipsOperandConverter FINAL : public InstructionOperandConverter {
}; };
static inline bool HasRegisterInput(Instruction* instr, int index) { static inline bool HasRegisterInput(Instruction* instr, size_t index) {
return instr->InputAt(index)->IsRegister(); return instr->InputAt(index)->IsRegister();
} }
@ -716,7 +716,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
break; break;
} }
case kMips64Swc1: { case kMips64Swc1: {
int index = 0; size_t index = 0;
MemOperand operand = i.MemoryOperand(&index); MemOperand operand = i.MemoryOperand(&index);
__ swc1(i.InputSingleRegister(index), operand); __ swc1(i.InputSingleRegister(index), operand);
break; break;