MIPS[64]: Disable Add/Shl to Lsa optimization if operand is immediate
Add/Shl to Lsa optimization doesn't yield any performance increase in case one of the operand is immediate, because Lsa cannot use the immediate so we use an extra instruction to load the immediate to register. On MIPSR2 and less this optimization leads to performance degradation, since Lsa is not supported on these architectures and it is emulated using Add/Shl which do support immediate as operand for Add. BUG= Review-Url: https://codereview.chromium.org/2509203003 Cr-Commit-Position: refs/heads/master@{#41143}
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@ -652,7 +652,7 @@ void InstructionSelector::VisitInt32Add(Node* node) {
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if (m.right().opcode() == IrOpcode::kWord32Shl &&
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if (m.right().opcode() == IrOpcode::kWord32Shl &&
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CanCover(node, m.left().node()) && CanCover(node, m.right().node())) {
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CanCover(node, m.left().node()) && CanCover(node, m.right().node())) {
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Int32BinopMatcher mright(m.right().node());
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Int32BinopMatcher mright(m.right().node());
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if (mright.right().HasValue()) {
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if (mright.right().HasValue() && !m.left().HasValue()) {
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int32_t shift_value = static_cast<int32_t>(mright.right().Value());
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int32_t shift_value = static_cast<int32_t>(mright.right().Value());
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Emit(kMipsLsa, g.DefineAsRegister(node), g.UseRegister(m.left().node()),
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Emit(kMipsLsa, g.DefineAsRegister(node), g.UseRegister(m.left().node()),
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g.UseRegister(mright.left().node()), g.TempImmediate(shift_value));
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g.UseRegister(mright.left().node()), g.TempImmediate(shift_value));
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@ -664,7 +664,7 @@ void InstructionSelector::VisitInt32Add(Node* node) {
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if (m.left().opcode() == IrOpcode::kWord32Shl &&
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if (m.left().opcode() == IrOpcode::kWord32Shl &&
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CanCover(node, m.right().node()) && CanCover(node, m.left().node())) {
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CanCover(node, m.right().node()) && CanCover(node, m.left().node())) {
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Int32BinopMatcher mleft(m.left().node());
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Int32BinopMatcher mleft(m.left().node());
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if (mleft.right().HasValue()) {
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if (mleft.right().HasValue() && !m.right().HasValue()) {
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int32_t shift_value = static_cast<int32_t>(mleft.right().Value());
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int32_t shift_value = static_cast<int32_t>(mleft.right().Value());
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Emit(kMipsLsa, g.DefineAsRegister(node), g.UseRegister(m.right().node()),
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Emit(kMipsLsa, g.DefineAsRegister(node), g.UseRegister(m.right().node()),
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g.UseRegister(mleft.left().node()), g.TempImmediate(shift_value));
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g.UseRegister(mleft.left().node()), g.TempImmediate(shift_value));
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@ -824,7 +824,7 @@ void InstructionSelector::VisitInt32Add(Node* node) {
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if (m.right().opcode() == IrOpcode::kWord32Shl &&
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if (m.right().opcode() == IrOpcode::kWord32Shl &&
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CanCover(node, m.left().node()) && CanCover(node, m.right().node())) {
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CanCover(node, m.left().node()) && CanCover(node, m.right().node())) {
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Int32BinopMatcher mright(m.right().node());
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Int32BinopMatcher mright(m.right().node());
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if (mright.right().HasValue()) {
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if (mright.right().HasValue() && !m.left().HasValue()) {
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int32_t shift_value = static_cast<int32_t>(mright.right().Value());
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int32_t shift_value = static_cast<int32_t>(mright.right().Value());
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Emit(kMips64Lsa, g.DefineAsRegister(node), g.UseRegister(m.left().node()),
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Emit(kMips64Lsa, g.DefineAsRegister(node), g.UseRegister(m.left().node()),
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g.UseRegister(mright.left().node()), g.TempImmediate(shift_value));
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g.UseRegister(mright.left().node()), g.TempImmediate(shift_value));
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@ -836,7 +836,7 @@ void InstructionSelector::VisitInt32Add(Node* node) {
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if (m.left().opcode() == IrOpcode::kWord32Shl &&
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if (m.left().opcode() == IrOpcode::kWord32Shl &&
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CanCover(node, m.right().node()) && CanCover(node, m.left().node())) {
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CanCover(node, m.right().node()) && CanCover(node, m.left().node())) {
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Int32BinopMatcher mleft(m.left().node());
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Int32BinopMatcher mleft(m.left().node());
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if (mleft.right().HasValue()) {
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if (mleft.right().HasValue() && !m.right().HasValue()) {
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int32_t shift_value = static_cast<int32_t>(mleft.right().Value());
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int32_t shift_value = static_cast<int32_t>(mleft.right().Value());
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Emit(kMips64Lsa, g.DefineAsRegister(node),
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Emit(kMips64Lsa, g.DefineAsRegister(node),
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g.UseRegister(m.right().node()), g.UseRegister(mleft.left().node()),
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g.UseRegister(m.right().node()), g.UseRegister(mleft.left().node()),
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@ -856,7 +856,7 @@ void InstructionSelector::VisitInt64Add(Node* node) {
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if (m.right().opcode() == IrOpcode::kWord64Shl &&
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if (m.right().opcode() == IrOpcode::kWord64Shl &&
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CanCover(node, m.left().node()) && CanCover(node, m.right().node())) {
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CanCover(node, m.left().node()) && CanCover(node, m.right().node())) {
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Int64BinopMatcher mright(m.right().node());
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Int64BinopMatcher mright(m.right().node());
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if (mright.right().HasValue()) {
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if (mright.right().HasValue() && !m.left().HasValue()) {
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int32_t shift_value = static_cast<int32_t>(mright.right().Value());
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int32_t shift_value = static_cast<int32_t>(mright.right().Value());
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Emit(kMips64Dlsa, g.DefineAsRegister(node),
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Emit(kMips64Dlsa, g.DefineAsRegister(node),
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g.UseRegister(m.left().node()), g.UseRegister(mright.left().node()),
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g.UseRegister(m.left().node()), g.UseRegister(mright.left().node()),
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@ -869,7 +869,7 @@ void InstructionSelector::VisitInt64Add(Node* node) {
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if (m.left().opcode() == IrOpcode::kWord64Shl &&
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if (m.left().opcode() == IrOpcode::kWord64Shl &&
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CanCover(node, m.right().node()) && CanCover(node, m.left().node())) {
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CanCover(node, m.right().node()) && CanCover(node, m.left().node())) {
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Int64BinopMatcher mleft(m.left().node());
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Int64BinopMatcher mleft(m.left().node());
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if (mleft.right().HasValue()) {
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if (mleft.right().HasValue() && !m.right().HasValue()) {
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int32_t shift_value = static_cast<int32_t>(mleft.right().Value());
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int32_t shift_value = static_cast<int32_t>(mleft.right().Value());
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Emit(kMips64Dlsa, g.DefineAsRegister(node),
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Emit(kMips64Dlsa, g.DefineAsRegister(node),
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g.UseRegister(m.right().node()), g.UseRegister(mleft.left().node()),
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g.UseRegister(m.right().node()), g.UseRegister(mleft.left().node()),
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