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[mips][wasm-simd] Implement f64x2 add sub mul div for mips

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Port 26afd8f314

Change-Id: I4033e6bb50166d59679dddd8ba0480b4bc4b821d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1874969
Commit-Queue: Mu Tao <pamilty@gmail.com>
Auto-Submit: Mu Tao <pamilty@gmail.com>
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64499}
This commit is contained in:
Mu Tao 2019-10-23 13:00:14 +08:00 committed by Commit Bot
parent 50784597e8
commit 5958b57ef4
8 changed files with 76 additions and 0 deletions
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26
src/compiler/backend/mips/code-generator-mips.cc
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@ -519,6 +519,12 @@ void EmitWordLoadPoisoningIfNeeded(CodeGenerator* codegen,
__ MovFromFloatResult(i.OutputDoubleRegister()); \
} while (0)
#define ASSEMBLE_F64X2_ARITHMETIC_BINOP(op) \
do { \
__ op(i.OutputSimd128Register(), i.InputSimd128Register(0), \
i.InputSimd128Register(1)); \
} while (0)
void CodeGenerator::AssembleDeconstructFrame() {
__ mov(sp, fp);
__ Pop(ra, fp);
@ -1957,6 +1963,26 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ fsqrt_d(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kMipsF64x2Add: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fadd_d);
break;
}
case kMipsF64x2Sub: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fsub_d);
break;
}
case kMipsF64x2Mul: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fmul_d);
break;
}
case kMipsF64x2Div: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fdiv_d);
break;
}
case kMipsF32x4Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ FmoveLow(kScratchReg, i.InputSingleRegister(0));

4
src/compiler/backend/mips/instruction-codes-mips.h
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@ -145,6 +145,10 @@ namespace compiler {
V(MipsF64x2Abs) \
V(MipsF64x2Neg) \
V(MipsF64x2Sqrt) \
V(MipsF64x2Add) \
V(MipsF64x2Sub) \
V(MipsF64x2Mul) \
V(MipsF64x2Div) \
V(MipsF32x4Splat) \
V(MipsF32x4ExtractLane) \
V(MipsF32x4ReplaceLane) \

4
src/compiler/backend/mips/instruction-scheduler-mips.cc
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@ -44,6 +44,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsF64x2Abs:
case kMipsF64x2Neg:
case kMipsF64x2Sqrt:
case kMipsF64x2Add:
case kMipsF64x2Sub:
case kMipsF64x2Mul:
case kMipsF64x2Div:
case kMipsF32x4Abs:
case kMipsF32x4Add:
case kMipsF32x4AddHoriz:

4
src/compiler/backend/mips/instruction-selector-mips.cc
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@ -2057,6 +2057,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16ShrU)
#define SIMD_BINOP_LIST(V) \
V(F64x2Add, kMipsF64x2Add) \
V(F64x2Sub, kMipsF64x2Sub) \
V(F64x2Mul, kMipsF64x2Mul) \
V(F64x2Div, kMipsF64x2Div) \
V(F32x4Add, kMipsF32x4Add) \
V(F32x4AddHoriz, kMipsF32x4AddHoriz) \
V(F32x4Sub, kMipsF32x4Sub) \

26
src/compiler/backend/mips64/code-generator-mips64.cc
View File

@ -490,6 +490,12 @@ void EmitWordLoadPoisoningIfNeeded(CodeGenerator* codegen,
__ MovFromFloatResult(i.OutputDoubleRegister()); \
} while (0)
#define ASSEMBLE_F64X2_ARITHMETIC_BINOP(op) \
do { \
__ op(i.OutputSimd128Register(), i.InputSimd128Register(0), \
i.InputSimd128Register(1)); \
} while (0)
void CodeGenerator::AssembleDeconstructFrame() {
__ mov(sp, fp);
__ Pop(ra, fp);
@ -2072,6 +2078,26 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ fsqrt_d(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kMips64F64x2Add: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fadd_d);
break;
}
case kMips64F64x2Sub: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fsub_d);
break;
}
case kMips64F64x2Mul: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fmul_d);
break;
}
case kMips64F64x2Div: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fdiv_d);
break;
}
case kMips64F32x4Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ FmoveLow(kScratchReg, i.InputSingleRegister(0));

4
src/compiler/backend/mips64/instruction-codes-mips64.h
View File

@ -190,6 +190,10 @@ namespace compiler {
V(Mips64I32x4MaxU) \
V(Mips64I32x4MinU) \
V(Mips64F64x2Sqrt) \
V(Mips64F64x2Add) \
V(Mips64F64x2Sub) \
V(Mips64F64x2Mul) \
V(Mips64F64x2Div) \
V(Mips64F32x4Abs) \
V(Mips64F32x4Neg) \
V(Mips64F32x4Sqrt) \

4
src/compiler/backend/mips64/instruction-scheduler-mips64.cc
View File

@ -72,6 +72,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64F64x2Abs:
case kMips64F64x2Neg:
case kMips64F64x2Sqrt:
case kMips64F64x2Add:
case kMips64F64x2Sub:
case kMips64F64x2Mul:
case kMips64F64x2Div:
case kMips64F32x4Abs:
case kMips64F32x4Add:
case kMips64F32x4AddHoriz:

4
src/compiler/backend/mips64/instruction-selector-mips64.cc
View File

@ -2720,6 +2720,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16ShrU)
#define SIMD_BINOP_LIST(V) \
V(F64x2Add, kMips64F64x2Add) \
V(F64x2Sub, kMips64F64x2Sub) \
V(F64x2Mul, kMips64F64x2Mul) \
V(F64x2Div, kMips64F64x2Div) \
V(F32x4Add, kMips64F32x4Add) \
V(F32x4AddHoriz, kMips64F32x4AddHoriz) \
V(F32x4Sub, kMips64F32x4Sub) \