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Fix '[tests] Don't test moves between different reps in test-gap-resolver.cc'

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Port fc59eb8a7a

Original commit message:
Moves between operands with different representations shouldn't happen,
so don't test them. This makes it easier to modify canonicalization to
differentiate between floating point types, which is needed to support
floating point register aliasing for ARM and MIPS.

This change also expands tests to include explicit FP moves (both register and stack slot).

LOG=N
BUG=v8:4124
BUG=chromium:622619

Review-Url: https://codereview.chromium.org/2090993002
Cr-Commit-Position: refs/heads/master@{#37241}
This commit is contained in:
balazs.kilvady 2016-06-24 01:23:52 -07:00 committed by Commit bot
parent 4b8128a051
commit 5cda2db7d3
13 changed files with 74 additions and 38 deletions
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9
src/arm/assembler-arm.h
View File

@ -119,7 +119,8 @@ struct Register {
return r;
}
const char* ToString();
bool IsAllocatable() const;
bool IsAllocatable(RegisterConfiguration::CompilerSelector compiler =
RegisterConfiguration::CRANKSHAFT) const;
bool is_valid() const { return 0 <= reg_code && reg_code < kNumRegisters; }
bool is(Register reg) const { return reg_code == reg.reg_code; }
int code() const {
@ -162,7 +163,8 @@ struct SwVfpRegister {
static const int kSizeInBytes = 4;
const char* ToString();
bool IsAllocatable() const;
bool IsAllocatable(RegisterConfiguration::CompilerSelector compiler =
RegisterConfiguration::CRANKSHAFT) const;
bool is_valid() const { return 0 <= reg_code && reg_code < 32; }
bool is(SwVfpRegister reg) const { return reg_code == reg.reg_code; }
int code() const {
@ -209,7 +211,8 @@ struct DwVfpRegister {
static const int kSizeInBytes = 8;
const char* ToString();
bool IsAllocatable() const;
bool IsAllocatable(RegisterConfiguration::CompilerSelector compiler =
RegisterConfiguration::CRANKSHAFT) const;
bool is_valid() const { return 0 <= reg_code && reg_code < kMaxNumRegisters; }
bool is(DwVfpRegister reg) const { return reg_code == reg.reg_code; }
int code() const {

6
src/arm64/assembler-arm64.h
View File

@ -155,7 +155,8 @@ struct Register : public CPURegister {
}
const char* ToString();
bool IsAllocatable() const;
bool IsAllocatable(RegisterConfiguration::CompilerSelector compiler =
RegisterConfiguration::CRANKSHAFT) const;
bool IsValid() const {
DCHECK(IsRegister() || IsNone());
return IsValidRegister();
@ -231,7 +232,8 @@ struct FPRegister : public CPURegister {
}
const char* ToString();
bool IsAllocatable() const;
bool IsAllocatable(RegisterConfiguration::CompilerSelector compiler =
RegisterConfiguration::CRANKSHAFT) const;
bool IsValid() const {
DCHECK(IsFPRegister() || IsNone());
return IsValidFPRegister();

15
src/assembler.cc
View File

@ -123,10 +123,10 @@ const char* Register::ToString() {
->GetGeneralRegisterName(reg_code);
}
bool Register::IsAllocatable() const {
bool Register::IsAllocatable(
RegisterConfiguration::CompilerSelector compiler) const {
return ((1 << reg_code) &
RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT)
RegisterConfiguration::ArchDefault(compiler)
->allocatable_general_codes_mask()) != 0;
}
@ -137,10 +137,10 @@ const char* DoubleRegister::ToString() {
->GetDoubleRegisterName(reg_code);
}
bool DoubleRegister::IsAllocatable() const {
bool DoubleRegister::IsAllocatable(
RegisterConfiguration::CompilerSelector compiler) const {
return ((1 << reg_code) &
RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT)
RegisterConfiguration::ArchDefault(compiler)
->allocatable_double_codes_mask()) != 0;
}
@ -154,7 +154,8 @@ const char* FloatRegister::ToString() {
->GetFloatRegisterName(reg_code);
}
bool FloatRegister::IsAllocatable() const {
bool FloatRegister::IsAllocatable(
RegisterConfiguration::CompilerSelector compiler) const {
// TODO(bbudge) Update this once RegisterConfigutation handles aliasing.
return ((1 << reg_code) &
RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT)

1
src/assembler.h
View File

@ -39,6 +39,7 @@
#include "src/builtins.h"
#include "src/isolate.h"
#include "src/log.h"
#include "src/register-configuration.h"
#include "src/runtime/runtime.h"
namespace v8 {

11
src/compiler/instruction.cc
View File

@ -250,11 +250,14 @@ ExplicitOperand::ExplicitOperand(LocationKind kind, MachineRepresentation rep,
int index)
: LocationOperand(EXPLICIT, kind, rep, index) {
DCHECK_IMPLIES(kind == REGISTER && !IsFloatingPoint(rep),
Register::from_code(index).IsAllocatable());
DCHECK_IMPLIES(kind == REGISTER && (rep == MachineRepresentation::kFloat32),
FloatRegister::from_code(index).IsAllocatable());
Register::from_code(index).IsAllocatable(
RegisterConfiguration::TURBOFAN));
DCHECK_IMPLIES(kind == REGISTER && rep == MachineRepresentation::kFloat32,
FloatRegister::from_code(index).IsAllocatable(
RegisterConfiguration::TURBOFAN));
DCHECK_IMPLIES(kind == REGISTER && (rep == MachineRepresentation::kFloat64),
DoubleRegister::from_code(index).IsAllocatable());
DoubleRegister::from_code(index).IsAllocatable(
RegisterConfiguration::TURBOFAN));
}
Instruction::Instruction(InstructionCode opcode)

6
src/ia32/assembler-ia32.h
View File

@ -125,7 +125,8 @@ struct Register {
return r;
}
const char* ToString();
bool IsAllocatable() const;
bool IsAllocatable(RegisterConfiguration::CompilerSelector compiler =
RegisterConfiguration::CRANKSHAFT) const;
bool is_valid() const { return 0 <= reg_code && reg_code < kNumRegisters; }
bool is(Register reg) const { return reg_code == reg.reg_code; }
int code() const {
@ -165,7 +166,8 @@ struct XMMRegister {
return result;
}
bool IsAllocatable() const;
bool IsAllocatable(RegisterConfiguration::CompilerSelector compiler =
RegisterConfiguration::CRANKSHAFT) const;
bool is_valid() const { return 0 <= reg_code && reg_code < kMaxNumRegisters; }
int code() const {

6
src/mips/assembler-mips.h
View File

@ -126,7 +126,8 @@ struct Register {
return r;
}
const char* ToString();
bool IsAllocatable() const;
bool IsAllocatable(RegisterConfiguration::CompilerSelector compiler =
RegisterConfiguration::CRANKSHAFT) const;
bool is_valid() const { return 0 <= reg_code && reg_code < kNumRegisters; }
bool is(Register reg) const { return reg_code == reg.reg_code; }
int code() const {
@ -174,7 +175,8 @@ struct FPURegister {
// number of Double regs (64-bit regs, or FPU-reg-pairs).
const char* ToString();
bool IsAllocatable() const;
bool IsAllocatable(RegisterConfiguration::CompilerSelector compiler =
RegisterConfiguration::CRANKSHAFT) const;
bool is_valid() const { return 0 <= reg_code && reg_code < kMaxNumRegisters; }
bool is(FPURegister reg) const { return reg_code == reg.reg_code; }
FPURegister low() const {

6
src/mips64/assembler-mips64.h
View File

@ -126,7 +126,8 @@ struct Register {
}
const char* ToString();
bool IsAllocatable() const;
bool IsAllocatable(RegisterConfiguration::CompilerSelector compiler =
RegisterConfiguration::CRANKSHAFT) const;
bool is_valid() const { return 0 <= reg_code && reg_code < kNumRegisters; }
bool is(Register reg) const { return reg_code == reg.reg_code; }
int code() const {
@ -174,7 +175,8 @@ struct FPURegister {
// number of Double regs (64-bit regs, or FPU-reg-pairs).
const char* ToString();
bool IsAllocatable() const;
bool IsAllocatable(RegisterConfiguration::CompilerSelector compiler =
RegisterConfiguration::CRANKSHAFT) const;
bool is_valid() const { return 0 <= reg_code && reg_code < kMaxNumRegisters; }
bool is(FPURegister reg) const { return reg_code == reg.reg_code; }
FPURegister low() const {

6
src/ppc/assembler-ppc.h
View File

@ -167,7 +167,8 @@ struct Register {
return r;
}
const char* ToString();
bool IsAllocatable() const;
bool IsAllocatable(RegisterConfiguration::CompilerSelector compiler =
RegisterConfiguration::CRANKSHAFT) const;
bool is_valid() const { return 0 <= reg_code && reg_code < kNumRegisters; }
bool is(Register reg) const { return reg_code == reg.reg_code; }
int code() const {
@ -220,7 +221,8 @@ struct DoubleRegister {
static const int kMaxNumRegisters = kNumRegisters;
const char* ToString();
bool IsAllocatable() const;
bool IsAllocatable(RegisterConfiguration::CompilerSelector compiler =
RegisterConfiguration::CRANKSHAFT) const;
bool is_valid() const { return 0 <= reg_code && reg_code < kNumRegisters; }
bool is(DoubleRegister reg) const { return reg_code == reg.reg_code; }
int code() const {

6
src/s390/assembler-s390.h
View File

@ -146,7 +146,8 @@ struct Register {
}
const char* ToString();
bool IsAllocatable() const;
bool IsAllocatable(RegisterConfiguration::CompilerSelector compiler =
RegisterConfiguration::CRANKSHAFT) const;
bool is_valid() const { return 0 <= reg_code && reg_code < kNumRegisters; }
bool is(Register reg) const { return reg_code == reg.reg_code; }
int code() const {
@ -201,7 +202,8 @@ struct DoubleRegister {
static const int kMaxNumRegisters = kNumRegisters;
const char* ToString();
bool IsAllocatable() const;
bool IsAllocatable(RegisterConfiguration::CompilerSelector compiler =
RegisterConfiguration::CRANKSHAFT) const;
bool is_valid() const { return 0 <= reg_code && reg_code < kNumRegisters; }
bool is(DoubleRegister reg) const { return reg_code == reg.reg_code; }

6
src/x64/assembler-x64.h
View File

@ -118,7 +118,8 @@ struct Register {
return r;
}
const char* ToString();
bool IsAllocatable() const;
bool IsAllocatable(RegisterConfiguration::CompilerSelector compiler =
RegisterConfiguration::CRANKSHAFT) const;
bool is_valid() const { return 0 <= reg_code && reg_code < kNumRegisters; }
bool is(Register reg) const { return reg_code == reg.reg_code; }
int code() const {
@ -219,7 +220,8 @@ struct XMMRegister {
}
const char* ToString();
bool IsAllocatable() const;
bool IsAllocatable(RegisterConfiguration::CompilerSelector compiler =
RegisterConfiguration::CRANKSHAFT) const;
bool is_valid() const { return 0 <= reg_code && reg_code < kMaxNumRegisters; }
bool is(XMMRegister reg) const { return reg_code == reg.reg_code; }
int code() const {

6
src/x87/assembler-x87.h
View File

@ -123,7 +123,8 @@ struct Register {
return r;
}
const char* ToString();
bool IsAllocatable() const;
bool IsAllocatable(RegisterConfiguration::CompilerSelector compiler =
RegisterConfiguration::CRANKSHAFT) const;
bool is_valid() const { return 0 <= reg_code && reg_code < kNumRegisters; }
bool is(Register reg) const { return reg_code == reg.reg_code; }
int code() const {
@ -164,7 +165,8 @@ struct X87Register {
return result;
}
bool IsAllocatable() const;
bool IsAllocatable(RegisterConfiguration::CompilerSelector compiler =
RegisterConfiguration::CRANKSHAFT) const;
bool is_valid() const { return 0 <= reg_code && reg_code < kMaxNumRegisters; }
int code() const {

28
test/cctest/compiler/test-gap-resolver.cc
View File

@ -200,6 +200,22 @@ class ParallelMoveCreator : public HandleAndZoneScope {
InstructionOperand CreateRandomOperand(bool is_source,
MachineRepresentation rep) {
auto conf =
RegisterConfiguration::ArchDefault(RegisterConfiguration::TURBOFAN);
auto GetRegisterCode = [&conf](MachineRepresentation rep, int index) {
switch (rep) {
case MachineRepresentation::kFloat32:
case MachineRepresentation::kFloat64:
return conf->RegisterConfiguration::GetAllocatableDoubleCode(index);
break;
default:
return conf->RegisterConfiguration::GetAllocatableGeneralCode(index);
break;
}
UNREACHABLE();
return static_cast<int>(Register::kCode_no_reg);
};
int index = rng_->NextInt(7);
// destination can't be Constant.
switch (rng_->NextInt(is_source ? 5 : 4)) {
@ -208,15 +224,11 @@ class ParallelMoveCreator : public HandleAndZoneScope {
case 1:
return AllocatedOperand(LocationOperand::REGISTER, rep, index);
case 2:
return ExplicitOperand(
LocationOperand::REGISTER, rep,
RegisterConfiguration::ArchDefault(RegisterConfiguration::TURBOFAN)
->GetAllocatableGeneralCode(1));
return ExplicitOperand(LocationOperand::REGISTER, rep,
GetRegisterCode(rep, 1));
case 3:
return ExplicitOperand(
LocationOperand::STACK_SLOT, rep,
RegisterConfiguration::ArchDefault(RegisterConfiguration::TURBOFAN)
->GetAllocatableGeneralCode(index));
return ExplicitOperand(LocationOperand::STACK_SLOT, rep,
GetRegisterCode(rep, index));
case 4:
return ConstantOperand(index);
}