Add ARMv6 support for the out-of-line constant pool.
R=ulan@chromium.org Review URL: https://codereview.chromium.org/496443003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23278 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
rmcilroy@chromium.org
parent
64eae3fc3c
commit
5dee3e0e2e
@ -423,36 +423,58 @@ void Assembler::emit(Instr x) {
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Address Assembler::target_address_from_return_address(Address pc) {
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// Returns the address of the call target from the return address that will
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// be returned to after a call.
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// Call sequence on V7 or later is :
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// Call sequence on V7 or later is:
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// movw ip, #... @ call address low 16
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// movt ip, #... @ call address high 16
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// blx ip
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// @ return address
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// Or pre-V7 or cases that need frequent patching, the address is in the
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// For V6 when the constant pool is unavailable, it is:
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// mov ip, #... @ call address low 8
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// orr ip, ip, #... @ call address 2nd 8
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// orr ip, ip, #... @ call address 3rd 8
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// orr ip, ip, #... @ call address high 8
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// blx ip
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// @ return address
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// In cases that need frequent patching, the address is in the
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// constant pool. It could be a small constant pool load:
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// ldr ip, [pc / pp, #...] @ call address
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// blx ip
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// @ return address
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// Or an extended constant pool load:
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// Or an extended constant pool load (ARMv7):
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// movw ip, #...
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// movt ip, #...
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// ldr ip, [pc, ip] @ call address
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// blx ip
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// @ return address
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// Or an extended constant pool load (ARMv6):
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// mov ip, #...
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// orr ip, ip, #...
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// orr ip, ip, #...
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// orr ip, ip, #...
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// ldr ip, [pc, ip] @ call address
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// blx ip
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// @ return address
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Address candidate = pc - 2 * Assembler::kInstrSize;
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Instr candidate_instr(Memory::int32_at(candidate));
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if (IsLdrPcImmediateOffset(candidate_instr) |
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IsLdrPpImmediateOffset(candidate_instr)) {
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return candidate;
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} else if (IsLdrPpRegOffset(candidate_instr)) {
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candidate = pc - 4 * Assembler::kInstrSize;
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DCHECK(IsMovW(Memory::int32_at(candidate)) &&
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IsMovT(Memory::int32_at(candidate + Assembler::kInstrSize)));
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return candidate;
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} else {
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candidate = pc - 3 * Assembler::kInstrSize;
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DCHECK(IsMovW(Memory::int32_at(candidate)) &&
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IsMovT(Memory::int32_at(candidate + kInstrSize)));
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if (IsLdrPpRegOffset(candidate_instr)) {
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candidate -= Assembler::kInstrSize;
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}
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if (CpuFeatures::IsSupported(ARMv7)) {
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candidate -= 1 * Assembler::kInstrSize;
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DCHECK(IsMovW(Memory::int32_at(candidate)) &&
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IsMovT(Memory::int32_at(candidate + Assembler::kInstrSize)));
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} else {
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candidate -= 3 * Assembler::kInstrSize;
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DCHECK(
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IsMovImmed(Memory::int32_at(candidate)) &&
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IsOrrImmed(Memory::int32_at(candidate + Assembler::kInstrSize)) &&
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IsOrrImmed(Memory::int32_at(candidate + 2 * Assembler::kInstrSize)) &&
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IsOrrImmed(Memory::int32_at(candidate + 3 * Assembler::kInstrSize)));
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}
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return candidate;
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}
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}
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@ -469,14 +491,28 @@ Address Assembler::return_address_from_call_start(Address pc) {
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// Load from constant pool, small section.
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return pc + kInstrSize * 2;
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} else {
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DCHECK(IsMovW(Memory::int32_at(pc)));
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DCHECK(IsMovT(Memory::int32_at(pc + kInstrSize)));
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if (IsLdrPpRegOffset(Memory::int32_at(pc + kInstrSize))) {
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// Load from constant pool, extended section.
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return pc + kInstrSize * 4;
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if (CpuFeatures::IsSupported(ARMv7)) {
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DCHECK(IsMovW(Memory::int32_at(pc)));
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DCHECK(IsMovT(Memory::int32_at(pc + kInstrSize)));
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if (IsLdrPpRegOffset(Memory::int32_at(pc + 2 * kInstrSize))) {
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// Load from constant pool, extended section.
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return pc + kInstrSize * 4;
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} else {
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// A movw / movt load immediate.
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return pc + kInstrSize * 3;
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}
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} else {
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// A movw / movt load immediate.
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return pc + kInstrSize * 3;
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DCHECK(IsMovImmed(Memory::int32_at(pc)));
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DCHECK(IsOrrImmed(Memory::int32_at(pc + kInstrSize)));
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DCHECK(IsOrrImmed(Memory::int32_at(pc + 2 * kInstrSize)));
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DCHECK(IsOrrImmed(Memory::int32_at(pc + 3 * kInstrSize)));
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if (IsLdrPpRegOffset(Memory::int32_at(pc + 4 * kInstrSize))) {
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// Load from constant pool, extended section.
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return pc + kInstrSize * 6;
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} else {
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// A mov / orr load immediate.
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return pc + kInstrSize * 5;
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}
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}
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}
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}
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@ -493,10 +529,17 @@ void Assembler::deserialization_set_special_target_at(
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bool Assembler::is_constant_pool_load(Address pc) {
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return !Assembler::IsMovW(Memory::int32_at(pc)) ||
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(FLAG_enable_ool_constant_pool &&
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Assembler::IsLdrPpRegOffset(
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Memory::int32_at(pc + 2 * Assembler::kInstrSize)));
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if (CpuFeatures::IsSupported(ARMv7)) {
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return !Assembler::IsMovW(Memory::int32_at(pc)) ||
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(FLAG_enable_ool_constant_pool &&
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Assembler::IsLdrPpRegOffset(
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Memory::int32_at(pc + 2 * Assembler::kInstrSize)));
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} else {
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return !Assembler::IsMovImmed(Memory::int32_at(pc)) ||
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(FLAG_enable_ool_constant_pool &&
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Assembler::IsLdrPpRegOffset(
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Memory::int32_at(pc + 4 * Assembler::kInstrSize)));
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}
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}
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@ -505,10 +548,22 @@ Address Assembler::constant_pool_entry_address(
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if (FLAG_enable_ool_constant_pool) {
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DCHECK(constant_pool != NULL);
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int cp_offset;
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if (IsMovW(Memory::int32_at(pc))) {
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if (!CpuFeatures::IsSupported(ARMv7) && IsMovImmed(Memory::int32_at(pc))) {
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DCHECK(IsOrrImmed(Memory::int32_at(pc + kInstrSize)) &&
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IsOrrImmed(Memory::int32_at(pc + 2 * kInstrSize)) &&
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IsOrrImmed(Memory::int32_at(pc + 3 * kInstrSize)) &&
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IsLdrPpRegOffset(Memory::int32_at(pc + 4 * kInstrSize)));
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// This is an extended constant pool lookup (ARMv6).
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Instr mov_instr = instr_at(pc);
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Instr orr_instr_1 = instr_at(pc + kInstrSize);
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Instr orr_instr_2 = instr_at(pc + 2 * kInstrSize);
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Instr orr_instr_3 = instr_at(pc + 3 * kInstrSize);
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cp_offset = DecodeShiftImm(mov_instr) | DecodeShiftImm(orr_instr_1) |
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DecodeShiftImm(orr_instr_2) | DecodeShiftImm(orr_instr_3);
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} else if (IsMovW(Memory::int32_at(pc))) {
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DCHECK(IsMovT(Memory::int32_at(pc + kInstrSize)) &&
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IsLdrPpRegOffset(Memory::int32_at(pc + 2 * kInstrSize)));
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// This is an extended constant pool lookup.
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// This is an extended constant pool lookup (ARMv7).
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Instruction* movw_instr = Instruction::At(pc);
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Instruction* movt_instr = Instruction::At(pc + kInstrSize);
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cp_offset = (movt_instr->ImmedMovwMovtValue() << 16) |
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@ -532,8 +587,8 @@ Address Assembler::target_address_at(Address pc,
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if (is_constant_pool_load(pc)) {
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// This is a constant pool lookup. Return the value in the constant pool.
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return Memory::Address_at(constant_pool_entry_address(pc, constant_pool));
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} else {
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// This is an movw_movt immediate load. Return the immediate.
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} else if (CpuFeatures::IsSupported(ARMv7)) {
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// This is an movw / movt immediate load. Return the immediate.
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DCHECK(IsMovW(Memory::int32_at(pc)) &&
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IsMovT(Memory::int32_at(pc + kInstrSize)));
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Instruction* movw_instr = Instruction::At(pc);
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@ -541,6 +596,20 @@ Address Assembler::target_address_at(Address pc,
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return reinterpret_cast<Address>(
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(movt_instr->ImmedMovwMovtValue() << 16) |
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movw_instr->ImmedMovwMovtValue());
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} else {
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// This is an mov / orr immediate load. Return the immediate.
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DCHECK(IsMovImmed(Memory::int32_at(pc)) &&
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IsOrrImmed(Memory::int32_at(pc + kInstrSize)) &&
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IsOrrImmed(Memory::int32_at(pc + 2 * kInstrSize)) &&
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IsOrrImmed(Memory::int32_at(pc + 3 * kInstrSize)));
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Instr mov_instr = instr_at(pc);
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Instr orr_instr_1 = instr_at(pc + kInstrSize);
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Instr orr_instr_2 = instr_at(pc + 2 * kInstrSize);
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Instr orr_instr_3 = instr_at(pc + 3 * kInstrSize);
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Address ret = reinterpret_cast<Address>(
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DecodeShiftImm(mov_instr) | DecodeShiftImm(orr_instr_1) |
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DecodeShiftImm(orr_instr_2) | DecodeShiftImm(orr_instr_3));
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return ret;
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}
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}
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@ -560,9 +629,9 @@ void Assembler::set_target_address_at(Address pc,
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// ldr ip, [pp, #...]
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// since the instruction accessing this address in the constant pool remains
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// unchanged.
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} else {
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// This is an movw_movt immediate load. Patch the immediate embedded in the
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// instructions.
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} else if (CpuFeatures::IsSupported(ARMv7)) {
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// This is an movw / movt immediate load. Patch the immediate embedded in
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// the instructions.
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DCHECK(IsMovW(Memory::int32_at(pc)));
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DCHECK(IsMovT(Memory::int32_at(pc + kInstrSize)));
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uint32_t* instr_ptr = reinterpret_cast<uint32_t*>(pc);
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@ -574,6 +643,26 @@ void Assembler::set_target_address_at(Address pc,
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if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
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CpuFeatures::FlushICache(pc, 2 * kInstrSize);
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}
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} else {
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// This is an mov / orr immediate load. Patch the immediate embedded in
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// the instructions.
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DCHECK(IsMovImmed(Memory::int32_at(pc)) &&
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IsOrrImmed(Memory::int32_at(pc + kInstrSize)) &&
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IsOrrImmed(Memory::int32_at(pc + 2 * kInstrSize)) &&
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IsOrrImmed(Memory::int32_at(pc + 3 * kInstrSize)));
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uint32_t* instr_ptr = reinterpret_cast<uint32_t*>(pc);
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uint32_t immediate = reinterpret_cast<uint32_t>(target);
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instr_ptr[0] = PatchShiftImm(instr_ptr[0], immediate & kImm8Mask);
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instr_ptr[1] = PatchShiftImm(instr_ptr[1], immediate & (kImm8Mask << 8));
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instr_ptr[2] = PatchShiftImm(instr_ptr[2], immediate & (kImm8Mask << 16));
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instr_ptr[3] = PatchShiftImm(instr_ptr[3], immediate & (kImm8Mask << 24));
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DCHECK(IsMovImmed(Memory::int32_at(pc)) &&
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IsOrrImmed(Memory::int32_at(pc + kInstrSize)) &&
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IsOrrImmed(Memory::int32_at(pc + 2 * kInstrSize)) &&
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IsOrrImmed(Memory::int32_at(pc + 3 * kInstrSize)));
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if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
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CpuFeatures::FlushICache(pc, 4 * kInstrSize);
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}
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}
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}
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@ -435,6 +435,10 @@ const Instr kMovLeaveCCPattern = 0x1a0 * B16;
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const Instr kMovwPattern = 0x30 * B20;
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const Instr kMovtPattern = 0x34 * B20;
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const Instr kMovwLeaveCCFlip = 0x5 * B21;
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const Instr kMovImmedMask = 0x7f * B21;
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const Instr kMovImmedPattern = 0x1d * B21;
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const Instr kOrrImmedMask = 0x7f * B21;
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const Instr kOrrImmedPattern = 0x1c * B21;
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const Instr kCmpCmnMask = 0xdd * B20 | 0xf * B12;
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const Instr kCmpCmnPattern = 0x15 * B20;
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const Instr kCmpCmnFlip = B21;
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@ -1052,9 +1056,6 @@ bool Operand::must_output_reloc_info(const Assembler* assembler) const {
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static bool use_mov_immediate_load(const Operand& x,
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const Assembler* assembler) {
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if (assembler != NULL && !assembler->is_constant_pool_available()) {
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// If there is no constant pool available, we must use an mov immediate.
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// TODO(rmcilroy): enable ARMv6 support.
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DCHECK(CpuFeatures::IsSupported(ARMv7));
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return true;
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} else if (CpuFeatures::IsSupported(MOVW_MOVT_IMMEDIATE_LOADS) &&
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(assembler == NULL || !assembler->predictable_code_size())) {
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@ -1081,11 +1082,14 @@ int Operand::instructions_required(const Assembler* assembler,
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// for the constant pool or immediate load
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int instructions;
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if (use_mov_immediate_load(*this, assembler)) {
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instructions = 2; // A movw, movt immediate load.
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// A movw / movt or mov / orr immediate load.
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instructions = CpuFeatures::IsSupported(ARMv7) ? 2 : 4;
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} else if (assembler != NULL && assembler->use_extended_constant_pool()) {
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instructions = 3; // An extended constant pool load.
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// An extended constant pool load.
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instructions = CpuFeatures::IsSupported(ARMv7) ? 3 : 5;
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} else {
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instructions = 1; // A small constant pool load.
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// A small constant pool load.
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instructions = 1;
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}
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if ((instr & ~kCondMask) != 13 * B21) { // mov, S not set
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@ -1107,21 +1111,27 @@ void Assembler::move_32_bit_immediate(Register rd,
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const Operand& x,
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Condition cond) {
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RelocInfo rinfo(pc_, x.rmode_, x.imm32_, NULL);
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uint32_t imm32 = static_cast<uint32_t>(x.imm32_);
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if (x.must_output_reloc_info(this)) {
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RecordRelocInfo(rinfo);
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}
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if (use_mov_immediate_load(x, this)) {
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Register target = rd.code() == pc.code() ? ip : rd;
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// TODO(rmcilroy): add ARMv6 support for immediate loads.
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DCHECK(CpuFeatures::IsSupported(ARMv7));
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if (!FLAG_enable_ool_constant_pool &&
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x.must_output_reloc_info(this)) {
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// Make sure the movw/movt doesn't get separated.
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BlockConstPoolFor(2);
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if (CpuFeatures::IsSupported(ARMv7)) {
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if (!FLAG_enable_ool_constant_pool && x.must_output_reloc_info(this)) {
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// Make sure the movw/movt doesn't get separated.
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BlockConstPoolFor(2);
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}
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movw(target, imm32 & 0xffff, cond);
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movt(target, imm32 >> 16, cond);
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} else {
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DCHECK(FLAG_enable_ool_constant_pool);
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mov(target, Operand(imm32 & kImm8Mask), LeaveCC, cond);
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orr(target, target, Operand(imm32 & (kImm8Mask << 8)), LeaveCC, cond);
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orr(target, target, Operand(imm32 & (kImm8Mask << 16)), LeaveCC, cond);
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orr(target, target, Operand(imm32 & (kImm8Mask << 24)), LeaveCC, cond);
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}
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movw(target, static_cast<uint32_t>(x.imm32_ & 0xffff), cond);
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movt(target, static_cast<uint32_t>(x.imm32_) >> 16, cond);
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if (target.code() != rd.code()) {
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mov(rd, target, LeaveCC, cond);
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}
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@ -1132,8 +1142,15 @@ void Assembler::move_32_bit_immediate(Register rd,
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DCHECK(FLAG_enable_ool_constant_pool);
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Register target = rd.code() == pc.code() ? ip : rd;
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// Emit instructions to load constant pool offset.
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movw(target, 0, cond);
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movt(target, 0, cond);
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if (CpuFeatures::IsSupported(ARMv7)) {
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movw(target, 0, cond);
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movt(target, 0, cond);
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} else {
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mov(target, Operand(0), LeaveCC, cond);
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orr(target, target, Operand(0), LeaveCC, cond);
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orr(target, target, Operand(0), LeaveCC, cond);
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orr(target, target, Operand(0), LeaveCC, cond);
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}
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// Load from constant pool at offset.
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ldr(rd, MemOperand(pp, target), cond);
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} else {
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@ -3147,6 +3164,22 @@ Instr Assembler::PatchMovwImmediate(Instr instruction, uint32_t immediate) {
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}
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int Assembler::DecodeShiftImm(Instr instr) {
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int rotate = Instruction::RotateValue(instr) * 2;
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int immed8 = Instruction::Immed8Value(instr);
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return (immed8 >> rotate) | (immed8 << (32 - rotate));
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}
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Instr Assembler::PatchShiftImm(Instr instr, int immed) {
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uint32_t rotate_imm = 0;
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uint32_t immed_8 = 0;
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bool immed_fits = fits_shifter(immed, &rotate_imm, &immed_8, NULL);
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DCHECK(immed_fits);
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return (instr & ~kOff12Mask) | (rotate_imm << 8) | immed_8;
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}
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bool Assembler::IsNop(Instr instr, int type) {
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DCHECK(0 <= type && type <= 14); // mov pc, pc isn't a nop.
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// Check for mov rx, rx where x = type.
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@ -3154,6 +3187,16 @@ bool Assembler::IsNop(Instr instr, int type) {
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}
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bool Assembler::IsMovImmed(Instr instr) {
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return (instr & kMovImmedMask) == kMovImmedPattern;
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}
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bool Assembler::IsOrrImmed(Instr instr) {
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return (instr & kOrrImmedMask) == kOrrImmedPattern;
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}
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// static
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bool Assembler::ImmediateFitsAddrMode1Instruction(int32_t imm32) {
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uint32_t dummy1;
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@ -3735,17 +3778,46 @@ void ConstantPoolBuilder::Populate(Assembler* assm,
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// Patch vldr/ldr instruction with correct offset.
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Instr instr = assm->instr_at(rinfo.pc());
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if (entry->section_ == ConstantPoolArray::EXTENDED_SECTION) {
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// Instructions to patch must be 'movw rd, [#0]' and 'movt rd, [#0].
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Instr next_instr = assm->instr_at(rinfo.pc() + Assembler::kInstrSize);
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DCHECK((Assembler::IsMovW(instr) &&
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Instruction::ImmedMovwMovtValue(instr) == 0));
|
||||
DCHECK((Assembler::IsMovT(next_instr) &&
|
||||
Instruction::ImmedMovwMovtValue(next_instr) == 0));
|
||||
assm->instr_at_put(rinfo.pc(),
|
||||
Assembler::PatchMovwImmediate(instr, offset & 0xffff));
|
||||
assm->instr_at_put(
|
||||
rinfo.pc() + Assembler::kInstrSize,
|
||||
Assembler::PatchMovwImmediate(next_instr, offset >> 16));
|
||||
if (CpuFeatures::IsSupported(ARMv7)) {
|
||||
// Instructions to patch must be 'movw rd, [#0]' and 'movt rd, [#0].
|
||||
Instr next_instr = assm->instr_at(rinfo.pc() + Assembler::kInstrSize);
|
||||
DCHECK((Assembler::IsMovW(instr) &&
|
||||
Instruction::ImmedMovwMovtValue(instr) == 0));
|
||||
DCHECK((Assembler::IsMovT(next_instr) &&
|
||||
Instruction::ImmedMovwMovtValue(next_instr) == 0));
|
||||
assm->instr_at_put(
|
||||
rinfo.pc(), Assembler::PatchMovwImmediate(instr, offset & 0xffff));
|
||||
assm->instr_at_put(
|
||||
rinfo.pc() + Assembler::kInstrSize,
|
||||
Assembler::PatchMovwImmediate(next_instr, offset >> 16));
|
||||
} else {
|
||||
// Instructions to patch must be 'mov rd, [#0]' and 'orr rd, rd, [#0].
|
||||
Instr instr_2 = assm->instr_at(rinfo.pc() + Assembler::kInstrSize);
|
||||
Instr instr_3 = assm->instr_at(rinfo.pc() + 2 * Assembler::kInstrSize);
|
||||
Instr instr_4 = assm->instr_at(rinfo.pc() + 3 * Assembler::kInstrSize);
|
||||
DCHECK((Assembler::IsMovImmed(instr) &&
|
||||
Instruction::Immed8Value(instr) == 0));
|
||||
DCHECK((Assembler::IsOrrImmed(instr_2) &&
|
||||
Instruction::Immed8Value(instr_2) == 0) &&
|
||||
Assembler::GetRn(instr_2).is(Assembler::GetRd(instr_2)));
|
||||
DCHECK((Assembler::IsOrrImmed(instr_3) &&
|
||||
Instruction::Immed8Value(instr_3) == 0) &&
|
||||
Assembler::GetRn(instr_3).is(Assembler::GetRd(instr_3)));
|
||||
DCHECK((Assembler::IsOrrImmed(instr_4) &&
|
||||
Instruction::Immed8Value(instr_4) == 0) &&
|
||||
Assembler::GetRn(instr_4).is(Assembler::GetRd(instr_4)));
|
||||
assm->instr_at_put(
|
||||
rinfo.pc(), Assembler::PatchShiftImm(instr, (offset & kImm8Mask)));
|
||||
assm->instr_at_put(
|
||||
rinfo.pc() + Assembler::kInstrSize,
|
||||
Assembler::PatchShiftImm(instr_2, (offset & (kImm8Mask << 8))));
|
||||
assm->instr_at_put(
|
||||
rinfo.pc() + 2 * Assembler::kInstrSize,
|
||||
Assembler::PatchShiftImm(instr_3, (offset & (kImm8Mask << 16))));
|
||||
assm->instr_at_put(
|
||||
rinfo.pc() + 3 * Assembler::kInstrSize,
|
||||
Assembler::PatchShiftImm(instr_4, (offset & (kImm8Mask << 24))));
|
||||
}
|
||||
} else if (type == ConstantPoolArray::INT64) {
|
||||
// Instruction to patch must be 'vldr rd, [pp, #0]'.
|
||||
DCHECK((Assembler::IsVldrDPpImmediateOffset(instr) &&
|
||||
|
||||
@ -1449,12 +1449,16 @@ class Assembler : public AssemblerBase {
|
||||
static Register GetCmpImmediateRegister(Instr instr);
|
||||
static int GetCmpImmediateRawImmediate(Instr instr);
|
||||
static bool IsNop(Instr instr, int type = NON_MARKING_NOP);
|
||||
static bool IsMovImmed(Instr instr);
|
||||
static bool IsOrrImmed(Instr instr);
|
||||
static bool IsMovT(Instr instr);
|
||||
static Instr GetMovTPattern();
|
||||
static bool IsMovW(Instr instr);
|
||||
static Instr GetMovWPattern();
|
||||
static Instr EncodeMovwImmediate(uint32_t immediate);
|
||||
static Instr PatchMovwImmediate(Instr instruction, uint32_t immediate);
|
||||
static int DecodeShiftImm(Instr instr);
|
||||
static Instr PatchShiftImm(Instr instr, int immed);
|
||||
|
||||
// Constants in pools are accessed via pc relative addressing, which can
|
||||
// reach +/-4KB for integer PC-relative loads and +/-1KB for floating-point
|
||||
|
||||
@ -564,7 +564,9 @@ class Instruction {
|
||||
inline int ShiftAmountValue() const { return Bits(11, 7); }
|
||||
// with immediate
|
||||
inline int RotateValue() const { return Bits(11, 8); }
|
||||
DECLARE_STATIC_ACCESSOR(RotateValue);
|
||||
inline int Immed8Value() const { return Bits(7, 0); }
|
||||
DECLARE_STATIC_ACCESSOR(Immed8Value);
|
||||
inline int Immed4Value() const { return Bits(19, 16); }
|
||||
inline int ImmedMovwMovtValue() const {
|
||||
return Immed4Value() << 12 | Offset12Value(); }
|
||||
|
||||
@ -346,7 +346,11 @@ void FullCodeGenerator::EmitProfilingCounterDecrement(int delta) {
|
||||
}
|
||||
|
||||
|
||||
#ifdef CAN_USE_ARMV7_INSTRUCTIONS
|
||||
static const int kProfileCounterResetSequenceLength = 5 * Assembler::kInstrSize;
|
||||
#else
|
||||
static const int kProfileCounterResetSequenceLength = 7 * Assembler::kInstrSize;
|
||||
#endif
|
||||
|
||||
|
||||
void FullCodeGenerator::EmitProfilingCounterReset() {
|
||||
@ -361,10 +365,13 @@ void FullCodeGenerator::EmitProfilingCounterReset() {
|
||||
reset_value = FLAG_interrupt_budget >> 4;
|
||||
}
|
||||
__ mov(r2, Operand(profiling_counter_));
|
||||
// The mov instruction above can be either 1, 2 or 3 instructions depending
|
||||
// upon whether it is an extended constant pool - insert nop to compensate.
|
||||
DCHECK(masm_->InstructionsGeneratedSince(&start) <= 3);
|
||||
while (masm_->InstructionsGeneratedSince(&start) != 3) {
|
||||
// The mov instruction above can be either 1 to 3 (for ARMv7) or 1 to 5
|
||||
// instructions (for ARMv6) depending upon whether it is an extended constant
|
||||
// pool - insert nop to compensate.
|
||||
int expected_instr_count =
|
||||
(kProfileCounterResetSequenceLength / Assembler::kInstrSize) - 2;
|
||||
DCHECK(masm_->InstructionsGeneratedSince(&start) <= expected_instr_count);
|
||||
while (masm_->InstructionsGeneratedSince(&start) != expected_instr_count) {
|
||||
__ nop();
|
||||
}
|
||||
__ mov(r3, Operand(Smi::FromInt(reset_value)));
|
||||
@ -4787,14 +4794,35 @@ static Address GetInterruptImmediateLoadAddress(Address pc) {
|
||||
DCHECK(Assembler::IsLdrPcImmediateOffset(Memory::int32_at(load_address)));
|
||||
} else if (Assembler::IsLdrPpRegOffset(Memory::int32_at(load_address))) {
|
||||
// This is an extended constant pool lookup.
|
||||
load_address -= 2 * Assembler::kInstrSize;
|
||||
DCHECK(Assembler::IsMovW(Memory::int32_at(load_address)));
|
||||
DCHECK(Assembler::IsMovT(
|
||||
Memory::int32_at(load_address + Assembler::kInstrSize)));
|
||||
} else if (Assembler::IsMovT(Memory::int32_at(load_address))) {
|
||||
// This is a movw_movt immediate load.
|
||||
if (CpuFeatures::IsSupported(ARMv7)) {
|
||||
load_address -= 2 * Assembler::kInstrSize;
|
||||
DCHECK(Assembler::IsMovW(Memory::int32_at(load_address)));
|
||||
DCHECK(Assembler::IsMovT(
|
||||
Memory::int32_at(load_address + Assembler::kInstrSize)));
|
||||
} else {
|
||||
load_address -= 4 * Assembler::kInstrSize;
|
||||
DCHECK(Assembler::IsMovImmed(Memory::int32_at(load_address)));
|
||||
DCHECK(Assembler::IsOrrImmed(
|
||||
Memory::int32_at(load_address + Assembler::kInstrSize)));
|
||||
DCHECK(Assembler::IsOrrImmed(
|
||||
Memory::int32_at(load_address + 2 * Assembler::kInstrSize)));
|
||||
DCHECK(Assembler::IsOrrImmed(
|
||||
Memory::int32_at(load_address + 3 * Assembler::kInstrSize)));
|
||||
}
|
||||
} else if (CpuFeatures::IsSupported(ARMv7) &&
|
||||
Assembler::IsMovT(Memory::int32_at(load_address))) {
|
||||
// This is a movw / movt immediate load.
|
||||
load_address -= Assembler::kInstrSize;
|
||||
DCHECK(Assembler::IsMovW(Memory::int32_at(load_address)));
|
||||
} else if (!CpuFeatures::IsSupported(ARMv7) &&
|
||||
Assembler::IsOrrImmed(Memory::int32_at(load_address))) {
|
||||
// This is a mov / orr immediate load.
|
||||
load_address -= 3 * Assembler::kInstrSize;
|
||||
DCHECK(Assembler::IsMovImmed(Memory::int32_at(load_address)));
|
||||
DCHECK(Assembler::IsOrrImmed(
|
||||
Memory::int32_at(load_address + Assembler::kInstrSize)));
|
||||
DCHECK(Assembler::IsOrrImmed(
|
||||
Memory::int32_at(load_address + 2 * Assembler::kInstrSize)));
|
||||
} else {
|
||||
// This is a small constant pool lookup.
|
||||
DCHECK(Assembler::IsLdrPpImmediateOffset(Memory::int32_at(load_address)));
|
||||
@ -4815,11 +4843,17 @@ void BackEdgeTable::PatchAt(Code* unoptimized_code,
|
||||
{
|
||||
// <decrement profiling counter>
|
||||
// bpl ok
|
||||
// ; load interrupt stub address into ip - either of:
|
||||
// ; load interrupt stub address into ip - either of (for ARMv7):
|
||||
// ; <small cp load> | <extended cp load> | <immediate load>
|
||||
// ldr ip, [pc/pp, #imm] | movw ip, #imm | movw ip, #imm
|
||||
// | movt ip, #imm> | movw ip, #imm
|
||||
// | movt ip, #imm | movw ip, #imm
|
||||
// | ldr ip, [pp, ip]
|
||||
// ; or (for ARMv6):
|
||||
// ; <small cp load> | <extended cp load> | <immediate load>
|
||||
// ldr ip, [pc/pp, #imm] | mov ip, #imm | mov ip, #imm
|
||||
// | orr ip, ip, #imm> | orr ip, ip, #imm
|
||||
// | orr ip, ip, #imm> | orr ip, ip, #imm
|
||||
// | orr ip, ip, #imm> | orr ip, ip, #imm
|
||||
// blx ip
|
||||
// <reset profiling counter>
|
||||
// ok-label
|
||||
@ -4836,11 +4870,17 @@ void BackEdgeTable::PatchAt(Code* unoptimized_code,
|
||||
case OSR_AFTER_STACK_CHECK:
|
||||
// <decrement profiling counter>
|
||||
// mov r0, r0 (NOP)
|
||||
// ; load on-stack replacement address into ip - either of:
|
||||
// ; load on-stack replacement address into ip - either of (for ARMv7):
|
||||
// ; <small cp load> | <extended cp load> | <immediate load>
|
||||
// ldr ip, [pc/pp, #imm] | movw ip, #imm | movw ip, #imm
|
||||
// | movt ip, #imm> | movw ip, #imm
|
||||
// | ldr ip, [pp, ip]
|
||||
// ; or (for ARMv6):
|
||||
// ; <small cp load> | <extended cp load> | <immediate load>
|
||||
// ldr ip, [pc/pp, #imm] | mov ip, #imm | mov ip, #imm
|
||||
// | orr ip, ip, #imm> | orr ip, ip, #imm
|
||||
// | orr ip, ip, #imm> | orr ip, ip, #imm
|
||||
// | orr ip, ip, #imm> | orr ip, ip, #imm
|
||||
// blx ip
|
||||
// <reset profiling counter>
|
||||
// ok-label
|
||||
|
||||
Loading…
Reference in New Issue
Block a user