AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

[riscv64] Port [fastcall] Support EnforceRange annotation

Browse Source 
Port commit 8559a04f4c

Change-Id: Ibeafd18e3bed0907536b93d1fd4c5db98bef41ba
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3746292
Commit-Queue: ji qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#81544}
This commit is contained in:
Lu Yahan 2022-07-06 09:12:39 +08:00 committed by V8 LUCI CQ
parent 9723c929f3
commit 600f753385
1 changed files with 30 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
src/compiler/backend/riscv64/instruction-selector-riscv64.cc
View File

@ -1268,6 +1268,36 @@ void InstructionSelector::VisitChangeFloat64ToInt32(Node* node) {
VisitRR(this, kRiscvTruncWD, node);
}
void InstructionSelector::VisitTryTruncateFloat64ToInt32(Node* node) {
RiscvOperandGenerator g(this);
InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0))};
InstructionOperand outputs[2];
size_t output_count = 0;
outputs[output_count++] = g.DefineAsRegister(node);
Node* success_output = NodeProperties::FindProjection(node, 1);
if (success_output) {
outputs[output_count++] = g.DefineAsRegister(success_output);
}
this->Emit(kRiscvTruncWD, output_count, outputs, 1, inputs);
}
void InstructionSelector::VisitTryTruncateFloat64ToUint32(Node* node) {
RiscvOperandGenerator g(this);
InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0))};
InstructionOperand outputs[2];
size_t output_count = 0;
outputs[output_count++] = g.DefineAsRegister(node);
Node* success_output = NodeProperties::FindProjection(node, 1);
if (success_output) {
outputs[output_count++] = g.DefineAsRegister(success_output);
}
Emit(kRiscvTruncUwD, output_count, outputs, 1, inputs);
}
void InstructionSelector::VisitChangeFloat64ToInt64(Node* node) {
VisitRR(this, kRiscvTruncLD, node);
}