From 622b1dc293628f0813a4cadf88e27e4923cc56ee Mon Sep 17 00:00:00 2001 From: Zhao Jiazhong Date: Wed, 11 Mar 2020 03:00:52 -0400 Subject: [PATCH] [mips][wasm-simd][liftoff] Implement add for f64x2, i64x2, i8x16 Port 485e66ba8e6196992d00283b03a49ea345706b9d https://crrev.com/c/2094198 Change-Id: I4e3ce2a70f2ccf4e95b0fa69834522d988e00f9b Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2097895 Reviewed-by: Zhi An Ng Reviewed-by: Clemens Backes Commit-Queue: Clemens Backes Cr-Commit-Position: refs/heads/master@{#66677} --- .../baseline/mips/liftoff-assembler-mips.h | 36 +++++++++++++++---- .../mips64/liftoff-assembler-mips64.h | 36 +++++++++++++++---- 2 files changed, 60 insertions(+), 12 deletions(-) diff --git a/src/wasm/baseline/mips/liftoff-assembler-mips.h b/src/wasm/baseline/mips/liftoff-assembler-mips.h index 9c8df3d02f..148238f341 100644 --- a/src/wasm/baseline/mips/liftoff-assembler-mips.h +++ b/src/wasm/baseline/mips/liftoff-assembler-mips.h @@ -1540,6 +1540,14 @@ void LiftoffAssembler::emit_f64x2_splat(LiftoffRegister dst, bailout(kSimd, "emit_f64x2_splat"); } +void LiftoffAssembler::emit_f64x2_add(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_f64x2_add"); +} + void LiftoffAssembler::emit_f32x4_splat(LiftoffRegister dst, LiftoffRegister src) { // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS @@ -1548,8 +1556,8 @@ void LiftoffAssembler::emit_f32x4_splat(LiftoffRegister dst, bailout(kSimd, "emit_f32x4_splat"); } -void LiftoffAssembler::emit_f32x4_add(LiftoffRegister dst, LiftoffRegister rhs, - LiftoffRegister lhs) { +void LiftoffAssembler::emit_f32x4_add(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming // 3a4000 support MSA. @@ -1564,6 +1572,14 @@ void LiftoffAssembler::emit_i64x2_splat(LiftoffRegister dst, bailout(kSimd, "emit_i64x2_splat"); } +void LiftoffAssembler::emit_i64x2_add(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i64x2_add"); +} + void LiftoffAssembler::emit_i32x4_splat(LiftoffRegister dst, LiftoffRegister src) { // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS @@ -1572,8 +1588,8 @@ void LiftoffAssembler::emit_i32x4_splat(LiftoffRegister dst, bailout(kSimd, "emit_i32x4_splat"); } -void LiftoffAssembler::emit_i32x4_add(LiftoffRegister dst, LiftoffRegister rhs, - LiftoffRegister lhs) { +void LiftoffAssembler::emit_i32x4_add(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming // 3a4000 support MSA. @@ -1588,8 +1604,8 @@ void LiftoffAssembler::emit_i16x8_splat(LiftoffRegister dst, bailout(kSimd, "emit_i16x8_splat"); } -void LiftoffAssembler::emit_i16x8_add(LiftoffRegister dst, LiftoffRegister rhs, - LiftoffRegister lhs) { +void LiftoffAssembler::emit_i16x8_add(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming // 3a4000 support MSA. @@ -1604,6 +1620,14 @@ void LiftoffAssembler::emit_i8x16_splat(LiftoffRegister dst, bailout(kSimd, "emit_i8x16_splat"); } +void LiftoffAssembler::emit_i8x16_add(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i8x16_add"); +} + void LiftoffAssembler::StackCheck(Label* ool_code, Register limit_address) { TurboAssembler::Ulw(limit_address, MemOperand(limit_address)); TurboAssembler::Branch(ool_code, ule, sp, Operand(limit_address)); diff --git a/src/wasm/baseline/mips64/liftoff-assembler-mips64.h b/src/wasm/baseline/mips64/liftoff-assembler-mips64.h index 56529276ce..72f707bda7 100644 --- a/src/wasm/baseline/mips64/liftoff-assembler-mips64.h +++ b/src/wasm/baseline/mips64/liftoff-assembler-mips64.h @@ -1332,6 +1332,14 @@ void LiftoffAssembler::emit_f64x2_splat(LiftoffRegister dst, bailout(kSimd, "emit_f64x2_splat"); } +void LiftoffAssembler::emit_f64x2_add(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_f64x2_add"); +} + void LiftoffAssembler::emit_f32x4_splat(LiftoffRegister dst, LiftoffRegister src) { // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS @@ -1340,8 +1348,8 @@ void LiftoffAssembler::emit_f32x4_splat(LiftoffRegister dst, bailout(kSimd, "emit_f32x4_splat"); } -void LiftoffAssembler::emit_f32x4_add(LiftoffRegister dst, LiftoffRegister rhs, - LiftoffRegister lhs) { +void LiftoffAssembler::emit_f32x4_add(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming // 3a4000 support MSA. @@ -1356,6 +1364,14 @@ void LiftoffAssembler::emit_i64x2_splat(LiftoffRegister dst, bailout(kSimd, "emit_i64x2_splat"); } +void LiftoffAssembler::emit_i64x2_add(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i64x2_add"); +} + void LiftoffAssembler::emit_i32x4_splat(LiftoffRegister dst, LiftoffRegister src) { // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS @@ -1364,8 +1380,8 @@ void LiftoffAssembler::emit_i32x4_splat(LiftoffRegister dst, bailout(kSimd, "emit_i32x4_splat"); } -void LiftoffAssembler::emit_i32x4_add(LiftoffRegister dst, LiftoffRegister rhs, - LiftoffRegister lhs) { +void LiftoffAssembler::emit_i32x4_add(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming // 3a4000 support MSA. @@ -1380,8 +1396,8 @@ void LiftoffAssembler::emit_i16x8_splat(LiftoffRegister dst, bailout(kSimd, "emit_i16x8_splat"); } -void LiftoffAssembler::emit_i16x8_add(LiftoffRegister dst, LiftoffRegister rhs, - LiftoffRegister lhs) { +void LiftoffAssembler::emit_i16x8_add(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming // 3a4000 support MSA. @@ -1396,6 +1412,14 @@ void LiftoffAssembler::emit_i8x16_splat(LiftoffRegister dst, bailout(kSimd, "emit_i8x16_splat"); } +void LiftoffAssembler::emit_i8x16_add(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i8x16_add"); +} + void LiftoffAssembler::StackCheck(Label* ool_code, Register limit_address) { TurboAssembler::Uld(limit_address, MemOperand(limit_address)); TurboAssembler::Branch(ool_code, ule, sp, Operand(limit_address));