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Add missing case for shr in IA-32 disassembler

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Review URL: http://codereview.chromium.org/397024

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3316 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
sgjesse@chromium.org 2009-11-17 10:24:27 +00:00
parent 459e4c6b0c
commit 63925e5013
2 changed files with 22 additions and 19 deletions
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40
src/ia32/disasm-ia32.cc
View File

@ -272,6 +272,17 @@ class DisassemblerIA32 {
}; };
enum ShiftOpcodeExtension {
kROL = 0,
kROR = 1,
kRCL = 2,
kRCR = 3,
kSHL = 4,
KSHR = 5,
kSAR = 7
};
const char* NameOfCPURegister(int reg) const { const char* NameOfCPURegister(int reg) const {
return converter_.NameOfCPURegister(reg); return converter_.NameOfCPURegister(reg);
} }
@ -536,31 +547,22 @@ int DisassemblerIA32::D1D3C1Instruction(byte* data) {
int num_bytes = 2; int num_bytes = 2;
if (mod == 3) { if (mod == 3) {
const char* mnem = NULL; const char* mnem = NULL;
switch (regop) {
case kROL: mnem = "rol"; break;
case kROR: mnem = "ror"; break;
case kRCL: mnem = "rcl"; break;
case kSHL: mnem = "shl"; break;
case KSHR: mnem = "shr"; break;
case kSAR: mnem = "sar"; break;
default: UnimplementedInstruction();
}
if (op == 0xD1) { if (op == 0xD1) {
imm8 = 1; imm8 = 1;
switch (regop) {
case edx: mnem = "rcl"; break;
case edi: mnem = "sar"; break;
case esp: mnem = "shl"; break;
default: UnimplementedInstruction();
}
} else if (op == 0xC1) { } else if (op == 0xC1) {
imm8 = *(data+2); imm8 = *(data+2);
num_bytes = 3; num_bytes = 3;
switch (regop) {
case edx: mnem = "rcl"; break;
case esp: mnem = "shl"; break;
case ebp: mnem = "shr"; break;
case edi: mnem = "sar"; break;
default: UnimplementedInstruction();
}
} else if (op == 0xD3) { } else if (op == 0xD3) {
switch (regop) { // Shift/rotate by cl.
case esp: mnem = "shl"; break;
case ebp: mnem = "shr"; break;
case edi: mnem = "sar"; break;
default: UnimplementedInstruction();
}
} }
ASSERT_NE(NULL, mnem); ASSERT_NE(NULL, mnem);
AppendToBuffer("%s %s,", mnem, NameOfCPURegister(rm)); AppendToBuffer("%s %s,", mnem, NameOfCPURegister(rm));

1
test/cctest/test-disasm-ia32.cc
View File

@ -201,6 +201,7 @@ TEST(DisasmIa320) {
__ shl(edx, 6); __ shl(edx, 6);
__ shl_cl(edx); __ shl_cl(edx);
__ shrd(edx, Operand(ebx, ecx, times_4, 10000)); __ shrd(edx, Operand(ebx, ecx, times_4, 10000));
__ shr(edx, 1);
__ shr(edx, 7); __ shr(edx, 7);
__ shr_cl(edx); __ shr_cl(edx);