From 63d1879d94634f050cefcb091ca1474bb9b05f11 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Thu, 27 Feb 2020 08:45:39 +0000 Subject: [PATCH] [wasm-simd][x64] Add AVX codegen for all true ops Bug: v8:9561 Change-Id: Ic57b38cefbdc21045d71601c67995d3568634c27 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2069400 Commit-Queue: Zhi An Ng Reviewed-by: Deepti Gandluri Cr-Commit-Position: refs/heads/master@{#66479} --- src/codegen/x64/assembler-x64.h | 4 ++-- src/codegen/x64/macro-assembler-x64.h | 3 +++ src/codegen/x64/sse-instr.h | 4 ++-- src/compiler/backend/x64/code-generator-x64.cc | 10 +++++----- src/diagnostics/x64/disasm-x64.cc | 4 ++-- test/cctest/test-disasm-x64.cc | 4 ++-- 6 files changed, 16 insertions(+), 13 deletions(-) diff --git a/src/codegen/x64/assembler-x64.h b/src/codegen/x64/assembler-x64.h index 380e120a17..fe3d6b2d2c 100644 --- a/src/codegen/x64/assembler-x64.h +++ b/src/codegen/x64/assembler-x64.h @@ -985,7 +985,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase { } SSE4_INSTRUCTION_LIST(DECLARE_SSE4_INSTRUCTION) - SSE4_PMOV_INSTRUCTION_LIST(DECLARE_SSE4_INSTRUCTION) + SSE4_UNOP_INSTRUCTION_LIST(DECLARE_SSE4_INSTRUCTION) DECLARE_SSE4_INSTRUCTION(blendvpd, 66, 0F, 38, 15) #undef DECLARE_SSE4_INSTRUCTION @@ -1061,7 +1061,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase { void v##instruction(XMMRegister dst, Operand src) { \ vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0); \ } - SSE4_PMOV_INSTRUCTION_LIST(DECLARE_SSE4_PMOV_AVX_INSTRUCTION) + SSE4_UNOP_INSTRUCTION_LIST(DECLARE_SSE4_PMOV_AVX_INSTRUCTION) #undef DECLARE_SSE4_PMOV_AVX_INSTRUCTION void movd(XMMRegister dst, Register src); diff --git a/src/codegen/x64/macro-assembler-x64.h b/src/codegen/x64/macro-assembler-x64.h index 7939a23271..d2cc4887f7 100644 --- a/src/codegen/x64/macro-assembler-x64.h +++ b/src/codegen/x64/macro-assembler-x64.h @@ -158,6 +158,8 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase { AVX_OP(Movss, movss) AVX_OP(Movsd, movsd) AVX_OP(Movdqu, movdqu) + AVX_OP(Pcmpeqb, pcmpeqb) + AVX_OP(Pcmpeqw, pcmpeqw) AVX_OP(Pcmpeqd, pcmpeqd) AVX_OP(Addss, addss) AVX_OP(Addsd, addsd) @@ -244,6 +246,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase { AVX_OP_SSE4_1(Insertps, insertps) AVX_OP_SSE4_1(Pinsrq, pinsrq) AVX_OP_SSE4_1(Pblendw, pblendw) + AVX_OP_SSE4_1(Ptest, ptest) AVX_OP_SSE4_1(Pmovsxbw, pmovsxbw) AVX_OP_SSE4_1(Pmovsxwd, pmovsxwd) AVX_OP_SSE4_1(Pmovsxdq, pmovsxdq) diff --git a/src/codegen/x64/sse-instr.h b/src/codegen/x64/sse-instr.h index a739e43d6e..74ec16d6a2 100644 --- a/src/codegen/x64/sse-instr.h +++ b/src/codegen/x64/sse-instr.h @@ -143,7 +143,6 @@ #define SSE4_INSTRUCTION_LIST(V) \ V(pcmpeqq, 66, 0F, 38, 29) \ - V(ptest, 66, 0F, 38, 17) \ V(packusdw, 66, 0F, 38, 2B) \ V(pminsb, 66, 0F, 38, 38) \ V(pminsd, 66, 0F, 38, 39) \ @@ -156,7 +155,8 @@ V(pmulld, 66, 0F, 38, 40) // SSE instructions whose AVX version has two operands. -#define SSE4_PMOV_INSTRUCTION_LIST(V) \ +#define SSE4_UNOP_INSTRUCTION_LIST(V) \ + V(ptest, 66, 0F, 38, 17) \ V(pmovsxbw, 66, 0F, 38, 20) \ V(pmovsxwd, 66, 0F, 38, 23) \ V(pmovsxdq, 66, 0F, 38, 25) \ diff --git a/src/compiler/backend/x64/code-generator-x64.cc b/src/compiler/backend/x64/code-generator-x64.cc index 48343f17b7..962428494b 100644 --- a/src/compiler/backend/x64/code-generator-x64.cc +++ b/src/compiler/backend/x64/code-generator-x64.cc @@ -595,9 +595,9 @@ void EmitWordLoadPoisoningIfNeeded(CodeGenerator* codegen, XMMRegister tmp2 = i.TempSimd128Register(1); \ __ movq(tmp1, Immediate(1)); \ __ xorq(dst, dst); \ - __ pxor(tmp2, tmp2); \ + __ Pxor(tmp2, tmp2); \ __ opcode(tmp2, i.InputSimd128Register(0)); \ - __ ptest(tmp2, tmp2); \ + __ Ptest(tmp2, tmp2); \ __ cmovq(zero, dst, tmp1); \ } while (false) @@ -3941,15 +3941,15 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( break; } case kX64S1x4AllTrue: { - ASSEMBLE_SIMD_ALL_TRUE(pcmpeqd); + ASSEMBLE_SIMD_ALL_TRUE(Pcmpeqd); break; } case kX64S1x8AllTrue: { - ASSEMBLE_SIMD_ALL_TRUE(pcmpeqw); + ASSEMBLE_SIMD_ALL_TRUE(Pcmpeqw); break; } case kX64S1x16AllTrue: { - ASSEMBLE_SIMD_ALL_TRUE(pcmpeqb); + ASSEMBLE_SIMD_ALL_TRUE(Pcmpeqb); break; } case kWord32AtomicExchangeInt8: { diff --git a/src/diagnostics/x64/disasm-x64.cc b/src/diagnostics/x64/disasm-x64.cc index 39fe81ae77..9a39fbff90 100644 --- a/src/diagnostics/x64/disasm-x64.cc +++ b/src/diagnostics/x64/disasm-x64.cc @@ -937,7 +937,7 @@ int DisassemblerX64::AVXInstruction(byte* data) { break; \ } SSSE3_UNOP_INSTRUCTION_LIST(DECLARE_SSE_UNOP_AVX_DIS_CASE) - SSE4_PMOV_INSTRUCTION_LIST(DECLARE_SSE_UNOP_AVX_DIS_CASE) + SSE4_UNOP_INSTRUCTION_LIST(DECLARE_SSE_UNOP_AVX_DIS_CASE) #undef DECLARE_SSE_UNOP_AVX_DIS_CASE default: @@ -1812,7 +1812,7 @@ int DisassemblerX64::TwoByteOpcodeInstruction(byte* data) { SSSE3_INSTRUCTION_LIST(SSE34_DIS_CASE) SSSE3_UNOP_INSTRUCTION_LIST(SSE34_DIS_CASE) SSE4_INSTRUCTION_LIST(SSE34_DIS_CASE) - SSE4_PMOV_INSTRUCTION_LIST(SSE34_DIS_CASE) + SSE4_UNOP_INSTRUCTION_LIST(SSE34_DIS_CASE) SSE4_2_INSTRUCTION_LIST(SSE34_DIS_CASE) #undef SSE34_DIS_CASE default: diff --git a/test/cctest/test-disasm-x64.cc b/test/cctest/test-disasm-x64.cc index ca60358332..acaabf8da2 100644 --- a/test/cctest/test-disasm-x64.cc +++ b/test/cctest/test-disasm-x64.cc @@ -572,7 +572,7 @@ TEST(DisasmX64) { __ blendvpd(xmm5, Operand(rdx, 4)); SSE4_INSTRUCTION_LIST(EMIT_SSE34_INSTR) - SSE4_PMOV_INSTRUCTION_LIST(EMIT_SSE34_INSTR) + SSE4_UNOP_INSTRUCTION_LIST(EMIT_SSE34_INSTR) SSE4_EXTRACT_INSTRUCTION_LIST(EMIT_SSE34_IMM_INSTR) } } @@ -751,7 +751,7 @@ TEST(DisasmX64) { notUsed4) \ __ v##instruction(xmm10, xmm1); \ __ v##instruction(xmm10, Operand(rdx, 4)); - SSE4_PMOV_INSTRUCTION_LIST(EMIT_SSE4_PMOV_AVXINSTR) + SSE4_UNOP_INSTRUCTION_LIST(EMIT_SSE4_PMOV_AVXINSTR) #undef EMIT_SSE4_PMOV_AVXINSTR #define EMIT_SSE2_SHIFT_IMM_AVX(instruction, notUsed1, notUsed2, notUsed3, \