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[wasm simd] Implement I64x2Eq and I64x2Ne for x64

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Bug: v8:8460
Change-Id: I8ab46f3bba5e298db717ce46c848ad2d7f753686
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1684425
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Michael Starzinger <mstarzinger@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Cr-Commit-Position: refs/heads/master@{#62520}
This commit is contained in:
Ng Zhi An 2019-07-03 09:12:53 -07:00 committed by Commit Bot
parent e6fb00029c
commit 64729e87e1
14 changed files with 53 additions and 0 deletions
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1
src/codegen/x64/sse-instr.h
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@ -68,6 +68,7 @@
V(psignd, 66, 0F, 38, 0A)
#define SSE4_INSTRUCTION_LIST(V) \
V(pcmpeqq, 66, 0F, 38, 29) \
V(ptest, 66, 0F, 38, 17) \
V(pmovsxbw, 66, 0F, 38, 20) \
V(pmovsxwd, 66, 0F, 38, 23) \

6
src/compiler/backend/instruction-selector.cc
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@ -1867,6 +1867,10 @@ void InstructionSelector::VisitNode(Node* node) {
return MarkAsSimd128(node), VisitI64x2Add(node);
case IrOpcode::kI64x2Sub:
return MarkAsSimd128(node), VisitI64x2Sub(node);
case IrOpcode::kI64x2Eq:
return MarkAsSimd128(node), VisitI64x2Eq(node);
case IrOpcode::kI64x2Ne:
return MarkAsSimd128(node), VisitI64x2Ne(node);
case IrOpcode::kI64x2ShrU:
return MarkAsSimd128(node), VisitI64x2ShrU(node);
case IrOpcode::kI32x4Splat:
@ -2522,6 +2526,8 @@ void InstructionSelector::VisitI64x2Shl(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2ShrS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2Add(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2Sub(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2Eq(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2Ne(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2ShrU(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_X64

14
src/compiler/backend/x64/code-generator-x64.cc
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@ -2477,6 +2477,20 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ psubq(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64I64x2Eq: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSE4_1);
__ pcmpeqq(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64I64x2Ne: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSE4_1);
__ pcmpeqq(i.OutputSimd128Register(), i.InputSimd128Register(1));
__ pcmpeqq(kScratchDoubleReg, kScratchDoubleReg);
__ pxor(i.OutputSimd128Register(), kScratchDoubleReg);
break;
}
case kX64I64x2ShrU: {
__ psrlq(i.OutputSimd128Register(), i.InputInt8(1));
break;

2
src/compiler/backend/x64/instruction-codes-x64.h
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@ -186,6 +186,8 @@ namespace compiler {
V(X64I64x2ShrS) \
V(X64I64x2Add) \
V(X64I64x2Sub) \
V(X64I64x2Eq) \
V(X64I64x2Ne) \
V(X64I64x2ShrU) \
V(X64I32x4Splat) \
V(X64I32x4ExtractLane) \

2
src/compiler/backend/x64/instruction-scheduler-x64.cc
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@ -152,6 +152,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kX64I64x2ShrS:
case kX64I64x2Add:
case kX64I64x2Sub:
case kX64I64x2Eq:
case kX64I64x2Ne:
case kX64I64x2ShrU:
case kX64I32x4Splat:
case kX64I32x4ExtractLane:

2
src/compiler/backend/x64/instruction-selector-x64.cc
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@ -2565,6 +2565,8 @@ VISIT_ATOMIC_BINOP(Xor)
V(F32x4Le) \
V(I64x2Add) \
V(I64x2Sub) \
V(I64x2Eq) \
V(I64x2Ne) \
V(I32x4Add) \
V(I32x4AddHoriz) \
V(I32x4Sub) \

2
src/compiler/machine-operator.cc
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@ -267,6 +267,8 @@ MachineType AtomicOpType(Operator const* op) {
V(I64x2Neg, Operator::kNoProperties, 1, 0, 1) \
V(I64x2Add, Operator::kCommutative, 2, 0, 1) \
V(I64x2Sub, Operator::kNoProperties, 2, 0, 1) \
V(I64x2Eq, Operator::kCommutative, 2, 0, 1) \
V(I64x2Ne, Operator::kCommutative, 2, 0, 1) \
V(I32x4Splat, Operator::kNoProperties, 1, 0, 1) \
V(I32x4SConvertF32x4, Operator::kNoProperties, 1, 0, 1) \
V(I32x4SConvertI16x8Low, Operator::kNoProperties, 1, 0, 1) \

2
src/compiler/machine-operator.h
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@ -498,6 +498,8 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
const Operator* I64x2ShrS(int32_t);
const Operator* I64x2Add();
const Operator* I64x2Sub();
const Operator* I64x2Eq();
const Operator* I64x2Ne();
const Operator* I64x2ShrU(int32_t);
const Operator* I32x4Splat();

2
src/compiler/opcodes.h
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@ -761,6 +761,8 @@
V(I64x2ShrS) \
V(I64x2Add) \
V(I64x2Sub) \
V(I64x2Eq) \
V(I64x2Ne) \
V(I64x2ShrU) \
V(I32x4Splat) \
V(I32x4ExtractLane) \

6
src/compiler/wasm-compiler.cc
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@ -4058,6 +4058,12 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode, Node* const* inputs) {
case wasm::kExprI64x2Sub:
return graph()->NewNode(mcgraph()->machine()->I64x2Sub(), inputs[0],
inputs[1]);
case wasm::kExprI64x2Eq:
return graph()->NewNode(mcgraph()->machine()->I64x2Eq(), inputs[0],
inputs[1]);
case wasm::kExprI64x2Ne:
return graph()->NewNode(mcgraph()->machine()->I64x2Ne(), inputs[0],
inputs[1]);
case wasm::kExprI32x4Splat:
return graph()->NewNode(mcgraph()->machine()->I32x4Splat(), inputs[0]);
case wasm::kExprI32x4SConvertF32x4:

2
src/wasm/wasm-interpreter.cc
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@ -2263,6 +2263,8 @@ class ThreadImpl {
CMPOP_CASE(F32x4Ge, f32x4, float4, int4, 4, a >= b)
CMPOP_CASE(F32x4Lt, f32x4, float4, int4, 4, a < b)
CMPOP_CASE(F32x4Le, f32x4, float4, int4, 4, a <= b)
CMPOP_CASE(I64x2Eq, i64x2, int2, int2, 2, a == b)
CMPOP_CASE(I64x2Ne, i64x2, int2, int2, 2, a != b)
CMPOP_CASE(I32x4Eq, i32x4, int4, int4, 4, a == b)
CMPOP_CASE(I32x4Ne, i32x4, int4, int4, 4, a != b)
CMPOP_CASE(I32x4GtS, i32x4, int4, int4, 4, a > b)

2
src/wasm/wasm-opcodes.cc
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@ -77,7 +77,9 @@ const char* WasmOpcodes::OpcodeName(WasmOpcode opcode) {
// Standard opcodes
CASE_INT_OP(Eqz, "eqz")
CASE_ALL_OP(Eq, "eq")
CASE_I64x2_OP(Eq, "eq")
CASE_ALL_OP(Ne, "ne")
CASE_I64x2_OP(Ne, "ne")
CASE_ALL_OP(Add, "add")
CASE_ALL_OP(Sub, "sub")
CASE_ALL_OP(Mul, "mul")

2
src/wasm/wasm-opcodes.h
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@ -305,6 +305,8 @@ bool IsJSCompatibleSignature(const FunctionSig* sig, bool hasBigIntFeature);
V(I32x4LeU, 0xfd33, s_ss) \
V(I32x4GeS, 0xfd34, s_ss) \
V(I32x4GeU, 0xfd35, s_ss) \
V(I64x2Eq, 0xfd36, s_ss) \
V(I64x2Ne, 0xfd37, s_ss) \
V(F32x4Eq, 0xfd40, s_ss) \
V(F32x4Ne, 0xfd41, s_ss) \
V(F32x4Lt, 0xfd42, s_ss) \

8
test/cctest/wasm/test-run-wasm-simd.cc
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@ -824,6 +824,14 @@ WASM_SIMD_TEST_NO_LOWERING(I64x2Sub) {
base::SubWithWraparound);
}
WASM_SIMD_TEST_NO_LOWERING(I64x2Eq) {
RunI64x2BinOpTest(execution_tier, lower_simd, kExprI64x2Eq, Equal);
}
WASM_SIMD_TEST_NO_LOWERING(I64x2Ne) {
RunI64x2BinOpTest(execution_tier, lower_simd, kExprI64x2Ne, NotEqual);
}
void RunI64x2ShiftOpTest(ExecutionTier execution_tier, LowerSimd lower_simd,
WasmOpcode opcode, Int64ShiftOp expected_op) {
for (int shift = 1; shift < 64; shift++) {