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MIPS: Fix missing Float32 case in AssembleArchBoolean.

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TEST=mjsunit/asm/embenchen/box2d
BUG=

Review URL: https://codereview.chromium.org/1234533004

Cr-Commit-Position: refs/heads/master@{#29608}
This commit is contained in:
dusan.milosavljevic 2015-07-13 06:32:53 -07:00 committed by Commit bot
parent 79a3cb2eac
commit 686e3abf66
2 changed files with 34 additions and 12 deletions
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23
src/compiler/mips/code-generator-mips.cc
View File

@ -263,8 +263,8 @@ Condition FlagsConditionToConditionOvf(FlagsCondition condition) {
return kNoCondition;
}
FPUCondition FlagsConditionToConditionCmpD(bool& predicate,
FlagsCondition condition) {
FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
FlagsCondition condition) {
switch (condition) {
case kEqual:
predicate = true;
@ -992,22 +992,33 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr,
__ Branch(USE_DELAY_SLOT, &done, cc, left, right);
__ li(result, Operand(1)); // In delay slot.
} else if (instr->arch_opcode() == kMipsCmpD) {
} else if (instr->arch_opcode() == kMipsCmpD ||
instr->arch_opcode() == kMipsCmpS) {
FPURegister left = i.InputDoubleRegister(0);
FPURegister right = i.InputDoubleRegister(1);
bool predicate;
FPUCondition cc = FlagsConditionToConditionCmpD(predicate, condition);
FPUCondition cc = FlagsConditionToConditionCmpFPU(predicate, condition);
if (!IsMipsArchVariant(kMips32r6)) {
__ li(result, Operand(1));
__ c(cc, D, left, right);
if (instr->arch_opcode() == kMipsCmpD) {
__ c(cc, D, left, right);
} else {
DCHECK(instr->arch_opcode() == kMipsCmpS);
__ c(cc, S, left, right);
}
if (predicate) {
__ Movf(result, zero_reg);
} else {
__ Movt(result, zero_reg);
}
} else {
__ cmp(cc, L, kDoubleCompareReg, left, right);
if (instr->arch_opcode() == kMipsCmpD) {
__ cmp(cc, L, kDoubleCompareReg, left, right);
} else {
DCHECK(instr->arch_opcode() == kMipsCmpS);
__ cmp(cc, W, kDoubleCompareReg, left, right);
}
__ mfc1(at, kDoubleCompareReg);
__ srl(result, at, 31); // Cmp returns all 1s for true.
if (!predicate) // Toggle result for not equal.

23
src/compiler/mips64/code-generator-mips64.cc
View File

@ -264,8 +264,8 @@ Condition FlagsConditionToConditionOvf(FlagsCondition condition) {
}
FPUCondition FlagsConditionToConditionCmpD(bool& predicate,
FlagsCondition condition) {
FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
FlagsCondition condition) {
switch (condition) {
case kEqual:
predicate = true;
@ -1061,22 +1061,33 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr,
cc = FlagsConditionToConditionCmp(condition);
__ Branch(USE_DELAY_SLOT, &done, cc, left, right);
__ li(result, Operand(1)); // In delay slot.
} else if (instr->arch_opcode() == kMips64CmpD) {
} else if (instr->arch_opcode() == kMips64CmpD ||
instr->arch_opcode() == kMips64CmpS) {
FPURegister left = i.InputDoubleRegister(0);
FPURegister right = i.InputDoubleRegister(1);
bool predicate;
FPUCondition cc = FlagsConditionToConditionCmpD(predicate, condition);
FPUCondition cc = FlagsConditionToConditionCmpFPU(predicate, condition);
if (kArchVariant != kMips64r6) {
__ li(result, Operand(1));
__ c(cc, D, left, right);
if (instr->arch_opcode() == kMips64CmpD) {
__ c(cc, D, left, right);
} else {
DCHECK(instr->arch_opcode() == kMips64CmpS);
__ c(cc, S, left, right);
}
if (predicate) {
__ Movf(result, zero_reg);
} else {
__ Movt(result, zero_reg);
}
} else {
__ cmp(cc, L, kDoubleCompareReg, left, right);
if (instr->arch_opcode() == kMips64CmpD) {
__ cmp(cc, L, kDoubleCompareReg, left, right);
} else {
DCHECK(instr->arch_opcode() == kMips64CmpS);
__ cmp(cc, W, kDoubleCompareReg, left, right);
}
__ dmfc1(at, kDoubleCompareReg);
__ dsrl32(result, at, 31); // Cmp returns all 1s for true.
if (!predicate) // Toggle result for not equal.