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[ia32][wasm] Add I16x8 Binop and CompareOp.

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Mul/MinS/MaxS/AddSaturateU/SubSaturateU/MinU/MaxU, Eq/Ne

Bug: 
Change-Id: I197712c37dcbc6648be5fd040ca23f2ea777a4f3
Reviewed-on: https://chromium-review.googlesource.com/760156
Commit-Queue: Jing Bao <jing.bao@intel.com>
Reviewed-by: Bill Budge <bbudge@chromium.org>
Reviewed-by: Benedikt Meurer <bmeurer@chromium.org>
Cr-Commit-Position: refs/heads/master@{#49395}
This commit is contained in:
jing.bao 2017-11-09 14:34:45 +08:00 committed by Commit Bot
parent 1adce94ab3
commit 69ab034892
6 changed files with 151 additions and 4 deletions
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97
src/compiler/ia32/code-generator-ia32.cc
View File

@ -2281,6 +2281,61 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputOperand(1));
break;
}
case kSSEI16x8Mul: {
__ pmullw(i.OutputSimd128Register(), i.InputOperand(1));
break;
}
case kAVXI16x8Mul: {
CpuFeatureScope avx_scope(tasm(), AVX);
__ vpmullw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputOperand(1));
break;
}
case kSSEI16x8MinS: {
__ pminsw(i.OutputSimd128Register(), i.InputOperand(1));
break;
}
case kAVXI16x8MinS: {
CpuFeatureScope avx_scope(tasm(), AVX);
__ vpminsw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputOperand(1));
break;
}
case kSSEI16x8MaxS: {
__ pmaxsw(i.OutputSimd128Register(), i.InputOperand(1));
break;
}
case kAVXI16x8MaxS: {
CpuFeatureScope avx_scope(tasm(), AVX);
__ vpmaxsw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputOperand(1));
break;
}
case kSSEI16x8Eq: {
__ pcmpeqw(i.OutputSimd128Register(), i.InputOperand(1));
break;
}
case kAVXI16x8Eq: {
CpuFeatureScope avx_scope(tasm(), AVX);
__ vpcmpeqw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputOperand(1));
break;
}
case kSSEI16x8Ne: {
__ pcmpeqw(i.OutputSimd128Register(), i.InputOperand(1));
__ pcmpeqw(kScratchDoubleReg, kScratchDoubleReg);
__ pxor(i.OutputSimd128Register(), kScratchDoubleReg);
break;
}
case kAVXI16x8Ne: {
CpuFeatureScope avx_scope(tasm(), AVX);
__ vpcmpeqw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputOperand(1));
__ vpcmpeqw(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg);
__ vpxor(i.OutputSimd128Register(), i.OutputSimd128Register(),
kScratchDoubleReg);
break;
}
case kSSEI16x8ShrU: {
__ psrlw(i.OutputSimd128Register(), i.InputInt8(1));
break;
@ -2291,6 +2346,48 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputInt8(1));
break;
}
case kSSEI16x8AddSaturateU: {
__ paddusw(i.OutputSimd128Register(), i.InputOperand(1));
break;
}
case kAVXI16x8AddSaturateU: {
CpuFeatureScope avx_scope(tasm(), AVX);
__ vpaddusw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputOperand(1));
break;
}
case kSSEI16x8SubSaturateU: {
__ psubusw(i.OutputSimd128Register(), i.InputOperand(1));
break;
}
case kAVXI16x8SubSaturateU: {
CpuFeatureScope avx_scope(tasm(), AVX);
__ vpsubusw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputOperand(1));
break;
}
case kSSEI16x8MinU: {
CpuFeatureScope sse_scope(tasm(), SSE4_1);
__ pminuw(i.OutputSimd128Register(), i.InputOperand(1));
break;
}
case kAVXI16x8MinU: {
CpuFeatureScope avx_scope(tasm(), AVX);
__ vpminuw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputOperand(1));
break;
}
case kSSEI16x8MaxU: {
CpuFeatureScope sse_scope(tasm(), SSE4_1);
__ pmaxuw(i.OutputSimd128Register(), i.InputOperand(1));
break;
}
case kAVXI16x8MaxU: {
CpuFeatureScope avx_scope(tasm(), AVX);
__ vpmaxuw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputOperand(1));
break;
}
case kIA32I8x16Splat: {
XMMRegister dst = i.OutputSimd128Register();
__ Movd(dst, i.InputOperand(0));

18
src/compiler/ia32/instruction-codes-ia32.h
View File

@ -164,8 +164,26 @@ namespace compiler {
V(AVXI16x8Sub) \
V(SSEI16x8SubSaturateS) \
V(AVXI16x8SubSaturateS) \
V(SSEI16x8Mul) \
V(AVXI16x8Mul) \
V(SSEI16x8MinS) \
V(AVXI16x8MinS) \
V(SSEI16x8MaxS) \
V(AVXI16x8MaxS) \
V(SSEI16x8Eq) \
V(AVXI16x8Eq) \
V(SSEI16x8Ne) \
V(AVXI16x8Ne) \
V(SSEI16x8ShrU) \
V(AVXI16x8ShrU) \
V(SSEI16x8AddSaturateU) \
V(AVXI16x8AddSaturateU) \
V(SSEI16x8SubSaturateU) \
V(AVXI16x8SubSaturateU) \
V(SSEI16x8MinU) \
V(AVXI16x8MinU) \
V(SSEI16x8MaxU) \
V(AVXI16x8MaxU) \
V(IA32I8x16Splat) \
V(IA32I8x16ExtractLane) \
V(SSEI8x16ReplaceLane) \

18
src/compiler/ia32/instruction-scheduler-ia32.cc
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@ -150,8 +150,26 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kAVXI16x8Sub:
case kSSEI16x8SubSaturateS:
case kAVXI16x8SubSaturateS:
case kSSEI16x8Mul:
case kAVXI16x8Mul:
case kSSEI16x8MinS:
case kAVXI16x8MinS:
case kSSEI16x8MaxS:
case kAVXI16x8MaxS:
case kSSEI16x8Eq:
case kAVXI16x8Eq:
case kSSEI16x8Ne:
case kAVXI16x8Ne:
case kSSEI16x8ShrU:
case kAVXI16x8ShrU:
case kSSEI16x8AddSaturateU:
case kAVXI16x8AddSaturateU:
case kSSEI16x8SubSaturateU:
case kAVXI16x8SubSaturateU:
case kSSEI16x8MinU:
case kAVXI16x8MinU:
case kSSEI16x8MaxU:
case kAVXI16x8MaxU:
case kIA32I8x16Splat:
case kIA32I8x16ExtractLane:
case kSSEI8x16ReplaceLane:

11
src/compiler/ia32/instruction-selector-ia32.cc
View File

@ -1919,7 +1919,16 @@ VISIT_ATOMIC_BINOP(Xor)
V(I16x8Add) \
V(I16x8AddSaturateS) \
V(I16x8Sub) \
V(I16x8SubSaturateS)
V(I16x8SubSaturateS) \
V(I16x8Mul) \
V(I16x8MinS) \
V(I16x8MaxS) \
V(I16x8Eq) \
V(I16x8Ne) \
V(I16x8AddSaturateU) \
V(I16x8SubSaturateU) \
V(I16x8MinU) \
V(I16x8MaxU)
#define SIMD_UNOP_LIST(V) V(I32x4Neg)

7
src/compiler/instruction-selector.cc
View File

@ -2250,7 +2250,7 @@ void InstructionSelector::VisitI16x8AddHoriz(Node* node) { UNIMPLEMENTED(); }
// && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64 && \
!V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
!V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitI16x8Mul(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8MinS(Node* node) { UNIMPLEMENTED(); }
@ -2272,7 +2272,12 @@ void InstructionSelector::VisitI16x8SubSaturateU(Node* node) {
void InstructionSelector::VisitI16x8MinU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8MaxU(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64
// && !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_MIPS &&
// !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64 && \
!V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitI16x8Neg(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64
// && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64

4
test/cctest/wasm/test-run-wasm-simd.cc
View File

@ -1201,8 +1201,6 @@ WASM_SIMD_TEST(I16x8SubSaturateS) {
RunI16x8BinOpTest(execution_mode, kExprI16x8SubSaturateS, SubSaturate);
}
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64 || \
V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
WASM_SIMD_TEST(I16x8Mul) {
RunI16x8BinOpTest(execution_mode, kExprI16x8Mul, Mul);
}
@ -1260,6 +1258,8 @@ WASM_SIMD_TEST(I16x8Ne) {
RunI16x8CompareOpTest(execution_mode, kExprI16x8Ne, NotEqual);
}
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64 || \
V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
WASM_SIMD_TEST(I16x8LtS) {
RunI16x8CompareOpTest(execution_mode, kExprI16x8LtS, Less);
}