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Clean up assembler for packed single-precision floats

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We already use PACKED_OP_LIST to generate AVX instructions, this change
reuses the same list to generate the SSE equivalents, by introducting a
helper assembler instruction, ps, as the actual implementation (similar
to out vps is used as the implementation for AVX packed
singled-precision floats).

Change-Id: I7dd72c2be75eb3ff5badf6d668780604cae8c684
Bug: v8:9396
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1834621
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64088}
This commit is contained in:
Ng Zhi An 2019-10-01 15:30:02 -07:00 committed by Commit Bot
parent cd89e2919a
commit 69bdc607fe
2 changed files with 22 additions and 92 deletions
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78
src/codegen/ia32/assembler-ia32.cc
View File

@ -2171,62 +2171,6 @@ void Assembler::xorpd(XMMRegister dst, Operand src) {
emit_sse_operand(dst, src);
}
void Assembler::andps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x54);
emit_sse_operand(dst, src);
}
void Assembler::andnps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x55);
emit_sse_operand(dst, src);
}
void Assembler::orps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x56);
emit_sse_operand(dst, src);
}
void Assembler::xorps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x57);
emit_sse_operand(dst, src);
}
void Assembler::addps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x58);
emit_sse_operand(dst, src);
}
void Assembler::subps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x5C);
emit_sse_operand(dst, src);
}
void Assembler::mulps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x59);
emit_sse_operand(dst, src);
}
void Assembler::divps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x5E);
emit_sse_operand(dst, src);
}
void Assembler::rcpps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
@ -2248,20 +2192,6 @@ void Assembler::rsqrtps(XMMRegister dst, Operand src) {
emit_sse_operand(dst, src);
}
void Assembler::minps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x5D);
emit_sse_operand(dst, src);
}
void Assembler::maxps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x5F);
emit_sse_operand(dst, src);
}
void Assembler::cmpps(XMMRegister dst, Operand src, uint8_t cmp) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
@ -2793,6 +2723,14 @@ void Assembler::minss(XMMRegister dst, Operand src) {
emit_sse_operand(dst, src);
}
// Packed single-precision floating-point SSE instructions.
void Assembler::ps(byte opcode, XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(opcode);
emit_sse_operand(dst, src);
}
// AVX instructions
void Assembler::vfmasd(byte op, XMMRegister dst, XMMRegister src1,
Operand src2) {

36
src/codegen/ia32/assembler-ia32.h
View File

@ -857,23 +857,6 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
void minss(XMMRegister dst, XMMRegister src) { minss(dst, Operand(src)); }
void minss(XMMRegister dst, Operand src);
void andps(XMMRegister dst, Operand src);
void andps(XMMRegister dst, XMMRegister src) { andps(dst, Operand(src)); }
void andnps(XMMRegister dst, Operand src);
void andnps(XMMRegister dst, XMMRegister src) { andnps(dst, Operand(src)); }
void xorps(XMMRegister dst, Operand src);
void xorps(XMMRegister dst, XMMRegister src) { xorps(dst, Operand(src)); }
void orps(XMMRegister dst, Operand src);
void orps(XMMRegister dst, XMMRegister src) { orps(dst, Operand(src)); }
void addps(XMMRegister dst, Operand src);
void addps(XMMRegister dst, XMMRegister src) { addps(dst, Operand(src)); }
void subps(XMMRegister dst, Operand src);
void subps(XMMRegister dst, XMMRegister src) { subps(dst, Operand(src)); }
void mulps(XMMRegister dst, Operand src);
void mulps(XMMRegister dst, XMMRegister src) { mulps(dst, Operand(src)); }
void divps(XMMRegister dst, Operand src);
void divps(XMMRegister dst, XMMRegister src) { divps(dst, Operand(src)); }
void rcpps(XMMRegister dst, Operand src);
void rcpps(XMMRegister dst, XMMRegister src) { rcpps(dst, Operand(src)); }
void sqrtps(XMMRegister dst, Operand src);
@ -887,11 +870,6 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
}
void sqrtpd(XMMRegister dst, XMMRegister src) { sqrtpd(dst, Operand(src)); }
void minps(XMMRegister dst, Operand src);
void minps(XMMRegister dst, XMMRegister src) { minps(dst, Operand(src)); }
void maxps(XMMRegister dst, Operand src);
void maxps(XMMRegister dst, XMMRegister src) { maxps(dst, Operand(src)); }
void cmpps(XMMRegister dst, Operand src, uint8_t cmp);
void cmpps(XMMRegister dst, XMMRegister src, uint8_t cmp) {
cmpps(dst, Operand(src), cmp);
@ -1511,6 +1489,9 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
}
void rorx(Register dst, Operand src, byte imm8);
// Implementation of packed single-precision floating-point SSE instructions.
void ps(byte op, XMMRegister dst, Operand src);
#define PACKED_OP_LIST(V) \
V(and, 0x54) \
V(andn, 0x55) \
@ -1523,6 +1504,15 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
V(div, 0x5e) \
V(max, 0x5f)
#define SSE_PACKED_OP_DECLARE(name, opcode) \
void name##ps(XMMRegister dst, XMMRegister src) { \
ps(opcode, dst, Operand(src)); \
} \
void name##ps(XMMRegister dst, Operand src) { ps(opcode, dst, src); }
PACKED_OP_LIST(SSE_PACKED_OP_DECLARE)
#undef SSE_PACKED_OP_DECLARE
#define AVX_PACKED_OP_DECLARE(name, opcode) \
void v##name##ps(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vps(opcode, dst, src1, Operand(src2)); \
@ -1538,6 +1528,8 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
}
PACKED_OP_LIST(AVX_PACKED_OP_DECLARE)
#undef AVX_PACKED_OP_DECLARE
#undef PACKED_OP_LIST
void vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
void vpd(byte op, XMMRegister dst, XMMRegister src1, Operand src2);