diff --git a/src/codegen/ppc/constants-ppc.h b/src/codegen/ppc/constants-ppc.h index 5435756043..306175e06d 100644 --- a/src/codegen/ppc/constants-ppc.h +++ b/src/codegen/ppc/constants-ppc.h @@ -385,7 +385,23 @@ using Instr = uint32_t; /* VSX Vector Convert Signed Fixed-Point Word to Single-Precision */ \ V(xvcvsxwsp, XVCVSXWSP, 0xF00002E0) \ /* VSX Vector Convert Unsigned Fixed-Point Word to Single-Precision */ \ - V(xvcvuxwsp, XVCVUXWSP, 0xF00002A0) + V(xvcvuxwsp, XVCVUXWSP, 0xF00002A0) \ + /* VSX Vector Round to Double-Precision Integer toward +Infinity */ \ + V(xvrdpip, XVRDPIP, 0xF00003A4) \ + /* VSX Vector Round to Double-Precision Integer toward -Infinity */ \ + V(xvrdpim, XVRDPIM, 0xF00003E4) \ + /* VSX Vector Round to Double-Precision Integer toward Zero */ \ + V(xvrdpiz, XVRDPIZ, 0xF0000364) \ + /* VSX Vector Round to Double-Precision Integer */ \ + V(xvrdpi, XVRDPI, 0xF0000324) \ + /* VSX Vector Round to Single-Precision Integer toward +Infinity */ \ + V(xvrspip, XVRSPIP, 0xF00002A4) \ + /* VSX Vector Round to Single-Precision Integer toward -Infinity */ \ + V(xvrspim, XVRSPIM, 0xF00002E4) \ + /* VSX Vector Round to Single-Precision Integer toward Zero */ \ + V(xvrspiz, XVRSPIZ, 0xF0000264) \ + /* VSX Vector Round to Single-Precision Integer */ \ + V(xvrspi, XVRSPI, 0xF0000224) #define PPC_XX2_OPCODE_UNUSED_LIST(V) \ /* VSX Scalar Square Root Double-Precision */ \ @@ -497,28 +513,12 @@ using Instr = uint32_t; V(xvnabsdp, XVNABSDP, 0xF00007A4) \ /* VSX Vector Negative Absolute Value Single-Precision */ \ V(xvnabssp, XVNABSSP, 0xF00006A4) \ - /* VSX Vector Round to Double-Precision Integer */ \ - V(xvrdpi, XVRDPI, 0xF0000324) \ /* VSX Vector Round to Double-Precision Integer using Current rounding */ \ /* mode */ \ V(xvrdpic, XVRDPIC, 0xF00003AC) \ - /* VSX Vector Round to Double-Precision Integer toward -Infinity */ \ - V(xvrdpim, XVRDPIM, 0xF00003E4) \ - /* VSX Vector Round to Double-Precision Integer toward +Infinity */ \ - V(xvrdpip, XVRDPIP, 0xF00003A4) \ - /* VSX Vector Round to Double-Precision Integer toward Zero */ \ - V(xvrdpiz, XVRDPIZ, 0xF0000364) \ - /* VSX Vector Round to Single-Precision Integer */ \ - V(xvrspi, XVRSPI, 0xF0000224) \ /* VSX Vector Round to Single-Precision Integer using Current rounding */ \ /* mode */ \ V(xvrspic, XVRSPIC, 0xF00002AC) \ - /* VSX Vector Round to Single-Precision Integer toward -Infinity */ \ - V(xvrspim, XVRSPIM, 0xF00002E4) \ - /* VSX Vector Round to Single-Precision Integer toward +Infinity */ \ - V(xvrspip, XVRSPIP, 0xF00002A4) \ - /* VSX Vector Round to Single-Precision Integer toward Zero */ \ - V(xvrspiz, XVRSPIZ, 0xF0000264) \ /* VSX Vector Reciprocal Square Root Estimate Double-Precision */ \ V(xvrsqrtedp, XVRSQRTEDP, 0xF0000328) \ /* VSX Vector Test for software Square Root Double-Precision */ \ diff --git a/src/compiler/backend/ppc/code-generator-ppc.cc b/src/compiler/backend/ppc/code-generator-ppc.cc index 9686fff00e..d475e42c16 100644 --- a/src/compiler/backend/ppc/code-generator-ppc.cc +++ b/src/compiler/backend/ppc/code-generator-ppc.cc @@ -3405,6 +3405,38 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( i.InputSimd128Register(1)); break; } + case kPPC_F64x2Ceil: { + __ xvrdpip(i.OutputSimd128Register(), i.InputSimd128Register(0)); + break; + } + case kPPC_F64x2Floor: { + __ xvrdpim(i.OutputSimd128Register(), i.InputSimd128Register(0)); + break; + } + case kPPC_F64x2Trunc: { + __ xvrdpiz(i.OutputSimd128Register(), i.InputSimd128Register(0)); + break; + } + case kPPC_F64x2NearestInt: { + __ xvrdpi(i.OutputSimd128Register(), i.InputSimd128Register(0)); + break; + } + case kPPC_F32x4Ceil: { + __ xvrspip(i.OutputSimd128Register(), i.InputSimd128Register(0)); + break; + } + case kPPC_F32x4Floor: { + __ xvrspim(i.OutputSimd128Register(), i.InputSimd128Register(0)); + break; + } + case kPPC_F32x4Trunc: { + __ xvrspiz(i.OutputSimd128Register(), i.InputSimd128Register(0)); + break; + } + case kPPC_F32x4NearestInt: { + __ xvrspi(i.OutputSimd128Register(), i.InputSimd128Register(0)); + break; + } case kPPC_StoreCompressTagged: { ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX); break; diff --git a/src/compiler/backend/ppc/instruction-codes-ppc.h b/src/compiler/backend/ppc/instruction-codes-ppc.h index c21a46fcbd..1c33d8b681 100644 --- a/src/compiler/backend/ppc/instruction-codes-ppc.h +++ b/src/compiler/backend/ppc/instruction-codes-ppc.h @@ -210,6 +210,10 @@ namespace compiler { V(PPC_F64x2Div) \ V(PPC_F64x2Min) \ V(PPC_F64x2Max) \ + V(PPC_F64x2Ceil) \ + V(PPC_F64x2Floor) \ + V(PPC_F64x2Trunc) \ + V(PPC_F64x2NearestInt) \ V(PPC_F32x4Splat) \ V(PPC_F32x4ExtractLane) \ V(PPC_F32x4ReplaceLane) \ @@ -231,6 +235,10 @@ namespace compiler { V(PPC_F32x4Div) \ V(PPC_F32x4Min) \ V(PPC_F32x4Max) \ + V(PPC_F32x4Ceil) \ + V(PPC_F32x4Floor) \ + V(PPC_F32x4Trunc) \ + V(PPC_F32x4NearestInt) \ V(PPC_I64x2Splat) \ V(PPC_I64x2ExtractLane) \ V(PPC_I64x2ReplaceLane) \ diff --git a/src/compiler/backend/ppc/instruction-scheduler-ppc.cc b/src/compiler/backend/ppc/instruction-scheduler-ppc.cc index aa8851d1b2..647ff6f679 100644 --- a/src/compiler/backend/ppc/instruction-scheduler-ppc.cc +++ b/src/compiler/backend/ppc/instruction-scheduler-ppc.cc @@ -133,6 +133,10 @@ int InstructionScheduler::GetTargetInstructionFlags( case kPPC_F64x2Div: case kPPC_F64x2Min: case kPPC_F64x2Max: + case kPPC_F64x2Ceil: + case kPPC_F64x2Floor: + case kPPC_F64x2Trunc: + case kPPC_F64x2NearestInt: case kPPC_F32x4Splat: case kPPC_F32x4ExtractLane: case kPPC_F32x4ReplaceLane: @@ -156,6 +160,10 @@ int InstructionScheduler::GetTargetInstructionFlags( case kPPC_F32x4Div: case kPPC_F32x4Min: case kPPC_F32x4Max: + case kPPC_F32x4Ceil: + case kPPC_F32x4Floor: + case kPPC_F32x4Trunc: + case kPPC_F32x4NearestInt: case kPPC_I64x2Splat: case kPPC_I64x2ExtractLane: case kPPC_I64x2ReplaceLane: diff --git a/src/compiler/backend/ppc/instruction-selector-ppc.cc b/src/compiler/backend/ppc/instruction-selector-ppc.cc index 5ba0be4e07..d41b39b367 100644 --- a/src/compiler/backend/ppc/instruction-selector-ppc.cc +++ b/src/compiler/backend/ppc/instruction-selector-ppc.cc @@ -2242,6 +2242,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) { V(F64x2Abs) \ V(F64x2Neg) \ V(F64x2Sqrt) \ + V(F64x2Ceil) \ + V(F64x2Floor) \ + V(F64x2Trunc) \ + V(F64x2NearestInt) \ V(F32x4Abs) \ V(F32x4Neg) \ V(F32x4RecipApprox) \ @@ -2249,6 +2253,10 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) { V(F32x4Sqrt) \ V(F32x4SConvertI32x4) \ V(F32x4UConvertI32x4) \ + V(F32x4Ceil) \ + V(F32x4Floor) \ + V(F32x4Trunc) \ + V(F32x4NearestInt) \ V(I64x2Neg) \ V(I32x4Neg) \ V(I32x4Abs) \ @@ -2417,22 +2425,6 @@ void InstructionSelector::VisitI16x8BitMask(Node* node) { UNIMPLEMENTED(); } void InstructionSelector::VisitI32x4BitMask(Node* node) { UNIMPLEMENTED(); } -void InstructionSelector::VisitF64x2Ceil(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitF64x2Floor(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitF64x2Trunc(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitF64x2NearestInt(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitF32x4Ceil(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitF32x4Floor(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitF32x4Trunc(Node* node) { UNIMPLEMENTED(); } - -void InstructionSelector::VisitF32x4NearestInt(Node* node) { UNIMPLEMENTED(); } - void InstructionSelector::EmitPrepareResults( ZoneVector* results, const CallDescriptor* call_descriptor, Node* node) {