[x64] Implement 256-bit assembly for SSSE3 UNOP instructions

Bug: v8:12228
Change-Id: I9312716f78e79fd0759c2f7adfef065b5df5cfda
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3275566
Reviewed-by: Zhi An Ng <zhin@chromium.org>
Commit-Queue: Yolanda Chen <yolanda.chen@intel.com>
Cr-Commit-Position: refs/heads/main@{#77861}
This commit is contained in:
Yolanda Chen 2021-11-12 06:21:48 +08:00 committed by V8 LUCI CQ
parent 4edbdee196
commit 7095cf14fa
3 changed files with 23 additions and 0 deletions

View File

@ -1156,6 +1156,12 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
} \
void v##instruction(XMMRegister dst, Operand src) { \
vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0); \
} \
void v##instruction(YMMRegister dst, YMMRegister src) { \
vinstr(0x##opcode, dst, ymm0, src, k##prefix, k##escape1##escape2, kW0); \
} \
void v##instruction(YMMRegister dst, Operand src) { \
vinstr(0x##opcode, dst, ymm0, src, k##prefix, k##escape1##escape2, kW0); \
}
SSSE3_UNOP_INSTRUCTION_LIST(DECLARE_SSSE3_UNOP_AVX_INSTRUCTION)

View File

@ -2719,6 +2719,10 @@ TEST(AssemblerX64Integer256bit) {
__ vpmaddubsw(ymm5, ymm7, ymm9);
__ vpsignd(ymm7, ymm0, ymm1);
__ vpmulhrsw(ymm4, ymm3, ymm1);
__ vpabsb(ymm1, ymm2);
__ vpabsb(ymm3, Operand(rbx, rcx, times_4, 10000));
__ vpabsw(ymm6, ymm5);
__ vpabsd(ymm7, ymm10);
// SSE4_AVX_INSTRUCTION
__ vpmuldq(ymm1, ymm5, ymm6);
@ -2769,6 +2773,14 @@ TEST(AssemblerX64Integer256bit) {
0xC4, 0xE2, 0x7D, 0x0A, 0xF9,
// vpmulhrsw ymm4, ymm3, ymm1
0xC4, 0xE2, 0x65, 0x0B, 0xE1,
// vpabsb ymm1, ymm2
0xC4, 0xE2, 0x7D, 0x1C, 0xCA,
// vpabsb ymm3, YMMWORD PTR [rbx+rcx+0x2710]
0xC4, 0xE2, 0x7D, 0x1C, 0x9C, 0x8b, 0x10, 0x27, 0x00, 0x00,
// vpabsw ymm6, ymm5
0xC4, 0xE2, 0x7D, 0x1D, 0xF5,
// vpabsd ymm7, ymm10
0xC4, 0xC2, 0x7D, 0x1E, 0xFA,
// SSE4_AVX_INSTRUCTION
// vpmuldq ymm1, ymm5, ymm6

View File

@ -1432,6 +1432,11 @@ UNINITIALIZED_TEST(DisasmX64YMMRegister) {
vpbroadcastd(ymm7, xmm8));
COMPARE("c4627d588c8b10270000 vpbroadcastd ymm9,[rbx+rcx*4+0x2710]",
vpbroadcastd(ymm9, Operand(rbx, rcx, times_4, 10000)));
COMPARE("c4e27d1cca vpabsb ymm1,ymm2", vpabsb(ymm1, ymm2));
COMPARE("c4e27d1c9c8b10270000 vpabsb ymm3,[rbx+rcx*4+0x2710]",
vpabsb(ymm3, Operand(rbx, rcx, times_4, 10000)));
COMPARE("c4e27d1df5 vpabsw ymm6,ymm5", vpabsw(ymm6, ymm5));
COMPARE("c4c27d1efa vpabsd ymm7,ymm10", vpabsd(ymm7, ymm10));
}
}