AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

[mips][wasm-simd] Implement f64x2 sqrt for mips

Browse Source 
Port 434f96812f

Change-Id: I9e9cb8b9ca56d5af3b5ffffa5908501c9214752d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1874968
Commit-Queue: Mu Tao <pamilty@gmail.com>
Auto-Submit: Mu Tao <pamilty@gmail.com>
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64497}
This commit is contained in:
Mu Tao 2019-10-23 11:15:46 +08:00 committed by Commit Bot
parent 6f1de28834
commit 720961bb39
8 changed files with 16 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/compiler/backend/mips/code-generator-mips.cc
View File

@ -1952,6 +1952,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ bnegi_d(i.OutputSimd128Register(), i.InputSimd128Register(0), 63);
break;
}
case kMipsF64x2Sqrt: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fsqrt_d(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kMipsF32x4Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ FmoveLow(kScratchReg, i.InputSingleRegister(0));

1
src/compiler/backend/mips/instruction-codes-mips.h
View File

@ -144,6 +144,7 @@ namespace compiler {
V(MipsI32x4Sub) \
V(MipsF64x2Abs) \
V(MipsF64x2Neg) \
V(MipsF64x2Sqrt) \
V(MipsF32x4Splat) \
V(MipsF32x4ExtractLane) \
V(MipsF32x4ReplaceLane) \

1
src/compiler/backend/mips/instruction-scheduler-mips.cc
View File

@ -43,6 +43,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsExt:
case kMipsF64x2Abs:
case kMipsF64x2Neg:
case kMipsF64x2Sqrt:
case kMipsF32x4Abs:
case kMipsF32x4Add:
case kMipsF32x4AddHoriz:

1
src/compiler/backend/mips/instruction-selector-mips.cc
View File

@ -2016,6 +2016,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
#define SIMD_UNOP_LIST(V) \
V(F64x2Abs, kMipsF64x2Abs) \
V(F64x2Neg, kMipsF64x2Neg) \
V(F64x2Sqrt, kMipsF64x2Sqrt) \
V(F32x4SConvertI32x4, kMipsF32x4SConvertI32x4) \
V(F32x4UConvertI32x4, kMipsF32x4UConvertI32x4) \
V(F32x4Abs, kMipsF32x4Abs) \

5
src/compiler/backend/mips64/code-generator-mips64.cc
View File

@ -2067,6 +2067,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ bnegi_d(i.OutputSimd128Register(), i.InputSimd128Register(0), 63);
break;
}
case kMips64F64x2Sqrt: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fsqrt_d(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kMips64F32x4Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ FmoveLow(kScratchReg, i.InputSingleRegister(0));

1
src/compiler/backend/mips64/instruction-codes-mips64.h
View File

@ -189,6 +189,7 @@ namespace compiler {
V(Mips64I32x4ShrU) \
V(Mips64I32x4MaxU) \
V(Mips64I32x4MinU) \
V(Mips64F64x2Sqrt) \
V(Mips64F32x4Abs) \
V(Mips64F32x4Neg) \
V(Mips64F32x4Sqrt) \

1
src/compiler/backend/mips64/instruction-scheduler-mips64.cc
View File

@ -71,6 +71,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64Ext:
case kMips64F64x2Abs:
case kMips64F64x2Neg:
case kMips64F64x2Sqrt:
case kMips64F32x4Abs:
case kMips64F32x4Add:
case kMips64F32x4AddHoriz:

1
src/compiler/backend/mips64/instruction-selector-mips64.cc
View File

@ -2679,6 +2679,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
#define SIMD_UNOP_LIST(V) \
V(F64x2Abs, kMips64F64x2Abs) \
V(F64x2Neg, kMips64F64x2Neg) \
V(F64x2Sqrt, kMips64F64x2Sqrt) \
V(F32x4SConvertI32x4, kMips64F32x4SConvertI32x4) \
V(F32x4UConvertI32x4, kMips64F32x4UConvertI32x4) \
V(F32x4Abs, kMips64F32x4Abs) \