[mips][wasm-simd] Implement integer absolute

Port 34f9bcdb82
https://crrev.com/c/2067845

Original Commit Message:

  Implements i8x16.abs, i16x8.abs, and i32x4.abs.

Change-Id: I95800caa298860326e3deadea2fce71640ae0227
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2086532
Reviewed-by: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Deepti Gandluri <gdeepti@chromium.org>
Cr-Commit-Position: refs/heads/master@{#66601}
This commit is contained in:
Zhao Jiazhong 2020-03-03 20:37:10 -05:00 committed by Commit Bot
parent 8f965daaf8
commit 72b02a0205
8 changed files with 54 additions and 0 deletions

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@ -2436,6 +2436,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(0));
break;
}
case kMipsI32x4Abs: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ asub_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128RegZero);
break;
}
case kMipsI16x8Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fill_h(i.OutputSimd128Register(), i.InputRegister(0));
@ -2597,6 +2603,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(0));
break;
}
case kMipsI16x8Abs: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ asub_s_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128RegZero);
break;
}
case kMipsI8x16Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fill_b(i.OutputSimd128Register(), i.InputRegister(0));
@ -2758,6 +2770,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(0));
break;
}
case kMipsI8x16Abs: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ asub_s_b(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128RegZero);
break;
}
case kMipsS128And: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ and_v(i.OutputSimd128Register(), i.InputSimd128Register(0),

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@ -203,6 +203,7 @@ namespace compiler {
V(MipsI32x4GeS) \
V(MipsI32x4GtU) \
V(MipsI32x4GeU) \
V(MipsI32x4Abs) \
V(MipsI16x8Splat) \
V(MipsI16x8ExtractLaneU) \
V(MipsI16x8ExtractLaneS) \
@ -230,6 +231,7 @@ namespace compiler {
V(MipsI16x8GtU) \
V(MipsI16x8GeU) \
V(MipsI16x8RoundingAverageU) \
V(MipsI16x8Abs) \
V(MipsI8x16Splat) \
V(MipsI8x16ExtractLaneU) \
V(MipsI8x16ExtractLaneS) \
@ -256,6 +258,7 @@ namespace compiler {
V(MipsI8x16GtU) \
V(MipsI8x16GeU) \
V(MipsI8x16RoundingAverageU) \
V(MipsI8x16Abs) \
V(MipsS128And) \
V(MipsS128Or) \
V(MipsS128Xor) \

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@ -137,6 +137,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsI16x8UConvertI32x4:
case kMipsI16x8UConvertI8x16High:
case kMipsI16x8UConvertI8x16Low:
case kMipsI16x8Abs:
case kMipsI32x4Add:
case kMipsI32x4AddHoriz:
case kMipsI32x4Eq:
@ -164,6 +165,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsI32x4UConvertF32x4:
case kMipsI32x4UConvertI16x8High:
case kMipsI32x4UConvertI16x8Low:
case kMipsI32x4Abs:
case kMipsI8x16Add:
case kMipsI8x16AddSaturateS:
case kMipsI8x16AddSaturateU:
@ -192,6 +194,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsI8x16SubSaturateS:
case kMipsI8x16SubSaturateU:
case kMipsI8x16UConvertI16x8:
case kMipsI8x16Abs:
case kMipsIns:
case kMipsLsa:
case kMipsMaddD:

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@ -2169,6 +2169,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I32x4GeS, kMipsI32x4GeS) \
V(I32x4GtU, kMipsI32x4GtU) \
V(I32x4GeU, kMipsI32x4GeU) \
V(I32x4Abs, kMipsI32x4Abs) \
V(I16x8Add, kMipsI16x8Add) \
V(I16x8AddSaturateS, kMipsI16x8AddSaturateS) \
V(I16x8AddSaturateU, kMipsI16x8AddSaturateU) \
@ -2190,6 +2191,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I16x8SConvertI32x4, kMipsI16x8SConvertI32x4) \
V(I16x8UConvertI32x4, kMipsI16x8UConvertI32x4) \
V(I16x8RoundingAverageU, kMipsI16x8RoundingAverageU) \
V(I16x8Abs, kMipsI16x8Abs) \
V(I8x16Add, kMipsI8x16Add) \
V(I8x16AddSaturateS, kMipsI8x16AddSaturateS) \
V(I8x16AddSaturateU, kMipsI8x16AddSaturateU) \
@ -2210,6 +2212,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16RoundingAverageU, kMipsI8x16RoundingAverageU) \
V(I8x16SConvertI16x8, kMipsI8x16SConvertI16x8) \
V(I8x16UConvertI16x8, kMipsI8x16UConvertI16x8) \
V(I8x16Abs, kMipsI8x16Abs) \
V(S128And, kMipsS128And) \
V(S128Or, kMipsS128Or) \
V(S128Xor, kMipsS128Xor) \

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@ -2490,6 +2490,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(0));
break;
}
case kMips64I32x4Abs: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ asub_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128RegZero);
break;
}
case kMips64I16x8Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fill_h(i.OutputSimd128Register(), i.InputRegister(0));
@ -2651,6 +2657,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(0));
break;
}
case kMips64I16x8Abs: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ asub_s_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128RegZero);
break;
}
case kMips64I8x16Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fill_b(i.OutputSimd128Register(), i.InputRegister(0));
@ -2812,6 +2824,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(0));
break;
}
case kMips64I8x16Abs: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ asub_s_b(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128RegZero);
break;
}
case kMips64S128And: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ and_v(i.OutputSimd128Register(), i.InputSimd128Register(0),

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@ -233,6 +233,7 @@ namespace compiler {
V(Mips64I32x4GeS) \
V(Mips64I32x4GtU) \
V(Mips64I32x4GeU) \
V(Mips64I32x4Abs) \
V(Mips64I16x8Splat) \
V(Mips64I16x8ExtractLaneU) \
V(Mips64I16x8ExtractLaneS) \
@ -260,6 +261,7 @@ namespace compiler {
V(Mips64I16x8GtU) \
V(Mips64I16x8GeU) \
V(Mips64I16x8RoundingAverageU) \
V(Mips64I16x8Abs) \
V(Mips64I8x16Splat) \
V(Mips64I8x16ExtractLaneU) \
V(Mips64I8x16ExtractLaneS) \
@ -286,6 +288,7 @@ namespace compiler {
V(Mips64I8x16GtU) \
V(Mips64I8x16GeU) \
V(Mips64I8x16RoundingAverageU) \
V(Mips64I8x16Abs) \
V(Mips64S128And) \
V(Mips64S128Or) \
V(Mips64S128Xor) \

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@ -167,6 +167,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64I16x8UConvertI8x16High:
case kMips64I16x8UConvertI8x16Low:
case kMips64I16x8RoundingAverageU:
case kMips64I16x8Abs:
case kMips64I32x4Add:
case kMips64I32x4AddHoriz:
case kMips64I32x4Eq:
@ -194,6 +195,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64I32x4UConvertF32x4:
case kMips64I32x4UConvertI16x8High:
case kMips64I32x4UConvertI16x8Low:
case kMips64I32x4Abs:
case kMips64I8x16Add:
case kMips64I8x16AddSaturateS:
case kMips64I8x16AddSaturateU:
@ -220,6 +222,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64I8x16SubSaturateS:
case kMips64I8x16SubSaturateU:
case kMips64I8x16RoundingAverageU:
case kMips64I8x16Abs:
case kMips64Ins:
case kMips64Lsa:
case kMips64MaxD:

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@ -2757,12 +2757,15 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I32x4SConvertI16x8High, kMips64I32x4SConvertI16x8High) \
V(I32x4UConvertI16x8Low, kMips64I32x4UConvertI16x8Low) \
V(I32x4UConvertI16x8High, kMips64I32x4UConvertI16x8High) \
V(I32x4Abs, kMips64I32x4Abs) \
V(I16x8Neg, kMips64I16x8Neg) \
V(I16x8SConvertI8x16Low, kMips64I16x8SConvertI8x16Low) \
V(I16x8SConvertI8x16High, kMips64I16x8SConvertI8x16High) \
V(I16x8UConvertI8x16Low, kMips64I16x8UConvertI8x16Low) \
V(I16x8UConvertI8x16High, kMips64I16x8UConvertI8x16High) \
V(I16x8Abs, kMips64I16x8Abs) \
V(I8x16Neg, kMips64I8x16Neg) \
V(I8x16Abs, kMips64I8x16Abs) \
V(S128Not, kMips64S128Not) \
V(S1x4AnyTrue, kMips64S1x4AnyTrue) \
V(S1x4AllTrue, kMips64S1x4AllTrue) \