[mips][Liftoff] Implement i64.clz and i64.ctz

port e554dec [Liftoff] https://crrev.com/c/1893343

Original Commit Message:

  These are two of the remaining missing instructions from the MVP.
  This CL adds support to {LiftoffCompiler} and provides assembly
  implementations for ia32, x64, arm, and arm64.

Change-Id: I9ebe177c4a8861c31f78af89d893cf9f2128b45b
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1898832
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Auto-Submit: Zhao Jiazhong <kyslie3100@gmail.com>
Cr-Commit-Position: refs/heads/master@{#64797}
This commit is contained in:
Zhao Jiazhong 2019-11-06 02:31:39 -05:00 committed by Commit Bot
parent 8b3b3bdb16
commit 732fd6cdc9
2 changed files with 42 additions and 0 deletions

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@ -864,6 +864,40 @@ void LiftoffAssembler::emit_i64_shr(LiftoffRegister dst, LiftoffRegister src,
kScratchReg);
}
void LiftoffAssembler::emit_i64_clz(LiftoffRegister dst, LiftoffRegister src) {
// return high == 0 ? 32 + CLZ32(low) : CLZ32(high);
Label done;
Label high_is_zero;
Branch(&high_is_zero, eq, src.high_gp(), Operand(zero_reg));
clz(dst.low_gp(), src.high_gp());
jmp(&done);
bind(&high_is_zero);
clz(dst.low_gp(), src.low_gp());
Addu(dst.low_gp(), dst.low_gp(), Operand(32));
bind(&done);
mov(dst.high_gp(), zero_reg); // High word of result is always 0.
}
void LiftoffAssembler::emit_i64_ctz(LiftoffRegister dst, LiftoffRegister src) {
// return low == 0 ? 32 + CTZ32(high) : CTZ32(low);
Label done;
Label low_is_zero;
Branch(&low_is_zero, eq, src.low_gp(), Operand(zero_reg));
Ctz(dst.low_gp(), src.low_gp());
jmp(&done);
bind(&low_is_zero);
Ctz(dst.low_gp(), src.high_gp());
Addu(dst.low_gp(), dst.low_gp(), Operand(32));
bind(&done);
mov(dst.high_gp(), zero_reg); // High word of result is always 0.
}
void LiftoffAssembler::emit_i32_to_intptr(Register dst, Register src) {
// This is a nop on mips32.
}

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@ -556,6 +556,14 @@ void LiftoffAssembler::FillStackSlotsWithZero(uint32_t index, uint32_t count) {
}
}
void LiftoffAssembler::emit_i64_clz(LiftoffRegister dst, LiftoffRegister src) {
Clz(dst.gp(), src.gp());
}
void LiftoffAssembler::emit_i64_ctz(LiftoffRegister dst, LiftoffRegister src) {
Ctz(dst.gp(), src.gp());
}
void LiftoffAssembler::emit_i32_mul(Register dst, Register lhs, Register rhs) {
TurboAssembler::Mul(dst, lhs, rhs);
}