From 7551eca9816a7386282789e806bafedb9d4817bd Mon Sep 17 00:00:00 2001 From: "balazs.kilvady" Date: Wed, 4 May 2016 04:42:12 -0700 Subject: [PATCH] MIPS64: Fix [turbofan] Length and index2 are unsigned in CheckedLoad/CheckedStore. Port b994ad45b089c64eb253f63526723ffc2a0c86c6 Original commit message: Also factor out test cases from test-run-machops.cc into test-run-load-store.cc TEST=cctest/test-run-load-store/RunLoadStoreZeroExtend64, cctest/test-run-load-store/RunOobCheckedLoadT_pseudo7, cctest/test-run-load-store/RunOobCheckedLoad_pseudo7 BUG=chromium:599717 LOG=Y Review-Url: https://codereview.chromium.org/1907363002 Cr-Commit-Position: refs/heads/master@{#36017} --- src/compiler/mips64/code-generator-mips64.cc | 20 ++++++++++--------- .../mips64/instruction-codes-mips64.h | 3 ++- .../mips64/instruction-selector-mips64.cc | 2 +- 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/src/compiler/mips64/code-generator-mips64.cc b/src/compiler/mips64/code-generator-mips64.cc index 73f1598237..db8adcec6b 100644 --- a/src/compiler/mips64/code-generator-mips64.cc +++ b/src/compiler/mips64/code-generator-mips64.cc @@ -359,7 +359,6 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate, } // namespace - #define ASSEMBLE_CHECKED_LOAD_FLOAT(width, asm_instr) \ do { \ auto result = i.Output##width##Register(); \ @@ -367,7 +366,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate, if (instr->InputAt(0)->IsRegister()) { \ auto offset = i.InputRegister(0); \ __ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \ - __ Daddu(kScratchReg, i.InputRegister(2), offset); \ + __ And(kScratchReg, offset, Operand(0xffffffff)); \ + __ Daddu(kScratchReg, i.InputRegister(2), kScratchReg); \ __ asm_instr(result, MemOperand(kScratchReg, 0)); \ } else { \ int offset = static_cast(i.InputOperand(0).immediate()); \ @@ -377,7 +377,6 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate, __ bind(ool->exit()); \ } while (0) - #define ASSEMBLE_CHECKED_LOAD_INTEGER(asm_instr) \ do { \ auto result = i.OutputRegister(); \ @@ -385,7 +384,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate, if (instr->InputAt(0)->IsRegister()) { \ auto offset = i.InputRegister(0); \ __ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \ - __ Daddu(kScratchReg, i.InputRegister(2), offset); \ + __ And(kScratchReg, offset, Operand(0xffffffff)); \ + __ Daddu(kScratchReg, i.InputRegister(2), kScratchReg); \ __ asm_instr(result, MemOperand(kScratchReg, 0)); \ } else { \ int offset = static_cast(i.InputOperand(0).immediate()); \ @@ -395,7 +395,6 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate, __ bind(ool->exit()); \ } while (0) - #define ASSEMBLE_CHECKED_STORE_FLOAT(width, asm_instr) \ do { \ Label done; \ @@ -403,7 +402,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate, auto offset = i.InputRegister(0); \ auto value = i.Input##width##Register(2); \ __ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \ - __ Daddu(kScratchReg, i.InputRegister(3), offset); \ + __ And(kScratchReg, offset, Operand(0xffffffff)); \ + __ Daddu(kScratchReg, i.InputRegister(3), kScratchReg); \ __ asm_instr(value, MemOperand(kScratchReg, 0)); \ } else { \ int offset = static_cast(i.InputOperand(0).immediate()); \ @@ -414,7 +414,6 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate, __ bind(&done); \ } while (0) - #define ASSEMBLE_CHECKED_STORE_INTEGER(asm_instr) \ do { \ Label done; \ @@ -422,7 +421,8 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate, auto offset = i.InputRegister(0); \ auto value = i.InputRegister(2); \ __ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \ - __ Daddu(kScratchReg, i.InputRegister(3), offset); \ + __ And(kScratchReg, offset, Operand(0xffffffff)); \ + __ Daddu(kScratchReg, i.InputRegister(3), kScratchReg); \ __ asm_instr(value, MemOperand(kScratchReg, 0)); \ } else { \ int offset = static_cast(i.InputOperand(0).immediate()); \ @@ -433,7 +433,6 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate, __ bind(&done); \ } while (0) - #define ASSEMBLE_ROUND_DOUBLE_TO_DOUBLE(mode) \ if (kArchVariant == kMips64r6) { \ __ cfc1(kScratchReg, FCSR); \ @@ -1491,6 +1490,9 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( case kMips64Lw: __ lw(i.OutputRegister(), i.MemoryOperand()); break; + case kMips64Lwu: + __ lwu(i.OutputRegister(), i.MemoryOperand()); + break; case kMips64Ld: __ ld(i.OutputRegister(), i.MemoryOperand()); break; diff --git a/src/compiler/mips64/instruction-codes-mips64.h b/src/compiler/mips64/instruction-codes-mips64.h index cb6df49096..6fd321ef02 100644 --- a/src/compiler/mips64/instruction-codes-mips64.h +++ b/src/compiler/mips64/instruction-codes-mips64.h @@ -116,9 +116,10 @@ namespace compiler { V(Mips64Lh) \ V(Mips64Lhu) \ V(Mips64Sh) \ - V(Mips64Ld) \ V(Mips64Lw) \ + V(Mips64Lwu) \ V(Mips64Sw) \ + V(Mips64Ld) \ V(Mips64Sd) \ V(Mips64Lwc1) \ V(Mips64Swc1) \ diff --git a/src/compiler/mips64/instruction-selector-mips64.cc b/src/compiler/mips64/instruction-selector-mips64.cc index f1cee60600..360dc69d62 100644 --- a/src/compiler/mips64/instruction-selector-mips64.cc +++ b/src/compiler/mips64/instruction-selector-mips64.cc @@ -158,7 +158,7 @@ void InstructionSelector::VisitLoad(Node* node) { opcode = load_rep.IsUnsigned() ? kMips64Lhu : kMips64Lh; break; case MachineRepresentation::kWord32: - opcode = kMips64Lw; + opcode = load_rep.IsUnsigned() ? kMips64Lwu : kMips64Lw; break; case MachineRepresentation::kTagged: // Fall through. case MachineRepresentation::kWord64: