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[x64] Verify disassembly of some AVX instructions

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Extract instructions, and pextrq.

Bug: v8:12207
Change-Id: I919ce53a6bb1357cb70d78b3c7f12fc3d2128deb
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3223969
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Cr-Commit-Position: refs/heads/main@{#77504}
This commit is contained in:
Ng Zhi An 2021-10-21 10:53:18 -07:00 committed by V8 LUCI CQ
parent eaa1ac794e
commit 76efd418e4
2 changed files with 15 additions and 12 deletions
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8
src/diagnostics/x64/disasm-x64.cc
View File

@ -1066,22 +1066,22 @@ int DisassemblerX64::AVXInstruction(byte* data) {
case 0x14:
AppendToBuffer("vpextrb ");
current += PrintRightByteOperand(current);
AppendToBuffer(",%s,0x%x,", NameOfAVXRegister(regop), *current++);
AppendToBuffer(",%s,0x%x", NameOfAVXRegister(regop), *current++);
break;
case 0x15:
AppendToBuffer("vpextrw ");
current += PrintRightOperand(current);
AppendToBuffer(",%s,0x%x,", NameOfAVXRegister(regop), *current++);
AppendToBuffer(",%s,0x%x", NameOfAVXRegister(regop), *current++);
break;
case 0x16:
AppendToBuffer("vpextr%c ", rex_w() ? 'q' : 'd');
current += PrintRightOperand(current);
AppendToBuffer(",%s,0x%x,", NameOfAVXRegister(regop), *current++);
AppendToBuffer(",%s,0x%x", NameOfAVXRegister(regop), *current++);
break;
case 0x17:
AppendToBuffer("vextractps ");
current += PrintRightOperand(current);
AppendToBuffer(",%s,0x%x,", NameOfAVXRegister(regop), *current++);
AppendToBuffer(",%s,0x%x", NameOfAVXRegister(regop), *current++);
break;
case 0x20:
AppendToBuffer("vpinsrb %s,%s,", NameOfAVXRegister(regop),

19
test/cctest/test-disasm-x64.cc
View File

@ -232,16 +232,8 @@ TEST(DisasmX64) {
__ vinsertps(xmm1, xmm2, xmm3, 1);
__ vinsertps(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 1);
__ vextractps(rax, xmm1, 1);
__ vlddqu(xmm1, Operand(rbx, rcx, times_4, 10000));
__ vpextrb(rax, xmm2, 12);
__ vpextrb(Operand(rbx, rcx, times_4, 10000), xmm2, 12);
__ vpextrw(rax, xmm2, 5);
__ vpextrw(Operand(rbx, rcx, times_4, 10000), xmm2, 5);
__ vpextrd(rax, xmm2, 2);
__ vpextrd(Operand(rbx, rcx, times_4, 10000), xmm2, 2);
__ vpextrq(rax, xmm2, 2);
__ vpinsrb(xmm1, xmm2, rax, 12);
__ vpinsrb(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 12);
@ -1307,6 +1299,17 @@ UNINITIALIZED_TEST(DisasmX64CheckOutputAVX) {
COMPARE_INSTR(exp, v##instruction(xmm9, xmm2, 21));
SSE2_INSTRUCTION_LIST_SHIFT_IMM(COMPARE_AVX_INSTR)
#undef COMPARE_AVX_INSTR
#define COMPARE_AVX_INSTR(instruction, reg) \
exp = "v" #instruction " " #reg ",xmm15,0x3"; \
COMPARE_INSTR(exp, v##instruction(rbx, xmm15, 3)); \
exp = "v" #instruction " [rax+0xa],xmm15,0x3"; \
COMPARE_INSTR(exp, v##instruction(Operand(rax, 10), xmm15, 3));
COMPARE_AVX_INSTR(extractps, rbx)
COMPARE_AVX_INSTR(pextrb, bl)
COMPARE_AVX_INSTR(pextrw, rbx)
COMPARE_INSTR("vpextrq rbx,xmm15,0x3", vpextrq(rbx, xmm15, 3));
#undef COMPARE_AVX_INSTR
}
UNINITIALIZED_TEST(DisasmX64YMMRegister) {