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[riscv64] Enable rvv on simulator

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Change-Id: I8b19de82af5e3f856f22b6f79d81dc6aee8a3d38
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3347231
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
Commit-Queue: ji qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#78420}
This commit is contained in:
Lu Yahan 2021-12-21 11:30:26 +08:00 committed by V8 LUCI CQ
parent 69c74cfa29
commit 792cd26e78
1 changed files with 1 additions and 1 deletions
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src/codegen/riscv64/assembler-riscv64.cc
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@ -57,7 +57,7 @@ static unsigned CpuFeaturesImpliedByCompiler() {
answer |= 1u << FPU;
#endif // def CAN_USE_FPU_INSTRUCTIONS
#if (defined CAN_USE_RVV_INSTRUCTIONS) && (defined USE_SIMULATOR)
#if (defined CAN_USE_RVV_INSTRUCTIONS) || (defined USE_SIMULATOR)
answer |= 1u << RISCV_SIMD;
#endif // def CAN_USE_RVV_INSTRUCTIONS && USE_SIMULATOR
return answer;