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[wasm-simd][liftoff] Fix SIMD reg code

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In both PrepareCall and ProcessParameter, we were incorrectly passing
the reg code of a Q register into LiftoffRegister::ForFpPair, which
takes a D register. Similar to the F32 case (the reg code was halved),
the reg code needs to be doubled (q1 -> d2) before constructing the
LiftoffRegister.

Bug: v8:9909
Change-Id: Id4df9e99b92546f68be0d99d98f0a1ac25ee7e5c
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2013492
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#65925}
This commit is contained in:
Ng Zhi An 2020-01-21 13:25:36 -08:00 committed by Commit Bot
parent 3bff8fa5ea
commit 7ae8c05530
2 changed files with 14 additions and 9 deletions
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5
src/wasm/baseline/liftoff-assembler.cc
View File

@ -655,7 +655,10 @@ void LiftoffAssembler::PrepareCall(FunctionSig* sig,
DCHECK_EQ(0, reg_code % 2);
reg = LiftoffRegister::from_code(rc, (reg_code / 2));
} else if (kNeedS128RegPair && type == kWasmS128) {
reg = LiftoffRegister::ForFpPair(DoubleRegister::from_code(reg_code));
// Similarly for double registers and SIMD registers, the SIMD code
// needs to be doubled to pass the f64 code to Liftoff.
reg = LiftoffRegister::ForFpPair(
DoubleRegister::from_code(reg_code * 2));
} else {
reg = LiftoffRegister::from_code(rc, reg_code);
}

18
src/wasm/baseline/liftoff-compiler.cc
View File

@ -416,16 +416,18 @@ class LiftoffCompiler {
if (param_loc.IsRegister()) {
DCHECK(!param_loc.IsAnyRegister());
int reg_code = param_loc.AsRegister();
#if V8_TARGET_ARCH_ARM
// Liftoff assumes a one-to-one mapping between float registers and
// double registers, and so does not distinguish between f32 and f64
// registers. The f32 register code must therefore be halved in order to
// pass the f64 code to Liftoff.
DCHECK_IMPLIES(type == kWasmF32, (reg_code % 2) == 0);
if (type == kWasmF32) {
if (!kSimpleFPAliasing && type == kWasmF32) {
// Liftoff assumes a one-to-one mapping between float registers and
// double registers, and so does not distinguish between f32 and f64
// registers. The f32 register code must therefore be halved in order
// to pass the f64 code to Liftoff.
DCHECK_EQ(0, reg_code % 2);
reg_code /= 2;
} else if (kNeedS128RegPair && type == kWasmS128) {
// Similarly for double registers and SIMD registers, the SIMD code
// needs to be doubled to pass the f64 code to Liftoff.
reg_code *= 2;
}
#endif
RegList cache_regs = rc == kGpReg ? kLiftoffAssemblerGpCacheRegs
: kLiftoffAssemblerFpCacheRegs;
if (cache_regs & (1ULL << reg_code)) {